disp.vhd

交流电压表相应的VHDL代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity disp is
  port(clk:in std_logic;
        d1,d2,d3:in std_logic_vector(3 downto 0);
        seg:out std_logic_vector(6 downto 0);
        ledh:out std_logic_vector(0 to 3)   );
end disp;

architecture rtl of disp is
  signal ss,dd1,dd2,dd3:std_logic_vector(3 downto 0);
  signal hy:std_logic_vector(0 to 3);
  signal count:std_logic_vector(1 downto 0);
  signal seg7: std_logic_vector(6 downto 0);
  
begin
   seg<=seg7;
   ledh<=hy;
   dd1<=d1;
   dd2<=d2;
   dd3<=d3;
     
   process(clk)
   begin
    if(clk'event and clk='1') then
     if(count=2)then
        count<="00";
      else  
        count<=count+1;
      end if;
    end if;
  end process;
process(count)
   variable a:std_logic_vector(1 downto 0);
  begin
     a:=count;
    case a is
       when"00"=>hy<="1001";
       when"01"=>hy<="0101";
       when"10"=>hy<="0010";
       when others=>hy<="0001";
    end case;
end process;
process(hy)
   variable b:std_logic_vector(0 to 3);
  begin
     b:=hy;
    case b is
       when"1001"=>ss<=dd1;
       when"0101"=>ss<=dd2;
       when"0010"=>ss<=dd3;
       when others=>ss<="1111";
    end case;
end process;
 process(ss)
   variable c:std_logic_vector(3 downto 0);
  begin
     c:=ss;
    case c is						--gfedcba
       when"0000"=>seg7<="1000000";
       when"0001"=>seg7<="1111001";
       when"0010"=>seg7<="0100100";
       when"0011"=>seg7<="0110000";
       when"0100"=>seg7<="0011001";
       when"0101"=>seg7<="0010010";
       when"0110"=>seg7<="0000010";
       when"0111"=>seg7<="1011000";
       when"1000"=>seg7<="0000000";
       when"1001"=>seg7<="0010000";
       when others=>seg7<="1111111";
    end case;
  end process; 
end  rtl;