decode_f9c.tdf

交流电压表相应的VHDL代码

--lpm_decode CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="FLEX10K" IGNORE_CASCADE_BUFFERS="OFF" LPM_DECODES=4 LPM_PIPELINE=0 LPM_WIDTH=2 data eq
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


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--synthesis_resources = lut 4 
SUBDESIGN decode_f9c
( 
	data[1..0]	:	input;
	eq[3..0]	:	output;
) 
VARIABLE
	cmpr1_aeb_int	:	WIRE;
	cmpr1_aeb	:	WIRE;
	cmpr1_dataa[1..0]	:	WIRE;
	cmpr1_datab[1..0]	:	WIRE;
	cmpr2_aeb_int	:	WIRE;
	cmpr2_aeb	:	WIRE;
	cmpr2_dataa[1..0]	:	WIRE;
	cmpr2_datab[1..0]	:	WIRE;
	cmpr3_aeb_int	:	WIRE;
	cmpr3_aeb	:	WIRE;
	cmpr3_dataa[1..0]	:	WIRE;
	cmpr3_datab[1..0]	:	WIRE;
	cmpr4_aeb_int	:	WIRE;
	cmpr4_aeb	:	WIRE;
	cmpr4_dataa[1..0]	:	WIRE;
	cmpr4_datab[1..0]	:	WIRE;
	const_data0w[1..0]	: WIRE;
	const_data1w[1..0]	: WIRE;
	const_data2w[1..0]	: WIRE;
	const_data3w[1..0]	: WIRE;
	eq_node[3..0]	: WIRE;

BEGIN 
	IF (cmpr1_dataa[] == cmpr1_datab[]) THEN
		cmpr1_aeb_int = VCC;
	ELSE
		cmpr1_aeb_int = GND;
	END IF;
	cmpr1_aeb = cmpr1_aeb_int;
	cmpr1_dataa[] = data[];
	cmpr1_datab[] = const_data0w[];
	IF (cmpr2_dataa[] == cmpr2_datab[]) THEN
		cmpr2_aeb_int = VCC;
	ELSE
		cmpr2_aeb_int = GND;
	END IF;
	cmpr2_aeb = cmpr2_aeb_int;
	cmpr2_dataa[] = data[];
	cmpr2_datab[] = const_data1w[];
	IF (cmpr3_dataa[] == cmpr3_datab[]) THEN
		cmpr3_aeb_int = VCC;
	ELSE
		cmpr3_aeb_int = GND;
	END IF;
	cmpr3_aeb = cmpr3_aeb_int;
	cmpr3_dataa[] = data[];
	cmpr3_datab[] = const_data2w[];
	IF (cmpr4_dataa[] == cmpr4_datab[]) THEN
		cmpr4_aeb_int = VCC;
	ELSE
		cmpr4_aeb_int = GND;
	END IF;
	cmpr4_aeb = cmpr4_aeb_int;
	cmpr4_dataa[] = data[];
	cmpr4_datab[] = const_data3w[];
	const_data0w[] = B"00";
	const_data1w[] = B"01";
	const_data2w[] = B"10";
	const_data3w[] = B"11";
	eq[] = eq_node[];
	eq_node[] = ( cmpr4_aeb, cmpr3_aeb, cmpr2_aeb, cmpr1_aeb);
END;
--VALID FILE