voltage.hier_info

交流电压表相应的VHDL代码

|voltage
clk => \clk_8khz:n[31].CLK
clk => \clk_8khz:n[30].CLK
clk => \clk_8khz:n[29].CLK
clk => \clk_8khz:n[28].CLK
clk => \clk_8khz:n[27].CLK
clk => \clk_8khz:n[26].CLK
clk => \clk_8khz:n[25].CLK
clk => \clk_8khz:n[24].CLK
clk => \clk_8khz:n[23].CLK
clk => \clk_8khz:n[22].CLK
clk => \clk_8khz:n[21].CLK
clk => \clk_8khz:n[20].CLK
clk => \clk_8khz:n[19].CLK
clk => \clk_8khz:n[18].CLK
clk => \clk_8khz:n[17].CLK
clk => \clk_8khz:n[16].CLK
clk => \clk_8khz:n[15].CLK
clk => \clk_8khz:n[14].CLK
clk => \clk_8khz:n[13].CLK
clk => \clk_8khz:n[12].CLK
clk => \clk_8khz:n[11].CLK
clk => \clk_8khz:n[10].CLK
clk => \clk_8khz:n[9].CLK
clk => \clk_8khz:n[8].CLK
clk => \clk_8khz:n[7].CLK
clk => \clk_8khz:n[6].CLK
clk => \clk_8khz:n[5].CLK
clk => \clk_8khz:n[4].CLK
clk => \clk_8khz:n[3].CLK
clk => \clk_8khz:n[2].CLK
clk => \clk_8khz:n[1].CLK
clk => \clk_8khz:n[0].CLK
clk => clk_8k.CLK
intr => x[7].ENA
intr => x[6].ENA
intr => x[5].ENA
intr => x[4].ENA
intr => x[3].ENA
intr => x[2].ENA
intr => x[1].ENA
intr => x[0].ENA
AD_data[0] => x[0].DATAIN
AD_data[1] => x[1].DATAIN
AD_data[2] => x[2].DATAIN
AD_data[3] => x[3].DATAIN
AD_data[4] => x[4].DATAIN
AD_data[5] => x[5].DATAIN
AD_data[6] => x[6].DATAIN
AD_data[7] => x[7].DATAIN
rd_wr <= clk_8k.DB_MAX_OUTPUT_PORT_TYPE
LED_point <= LED_point~reg0.DB_MAX_OUTPUT_PORT_TYPE
LED_data[0] <= LED_data[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[1] <= LED_data[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[2] <= LED_data[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[3] <= LED_data[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[4] <= LED_data[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[5] <= LED_data[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
LED_data[6] <= LED_data[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
sw[0] <= LPM_DECODE:scan_sw.EQ[0]
sw[1] <= LPM_DECODE:scan_sw.EQ[1]
sw[2] <= LPM_DECODE:scan_sw.EQ[2]
sw[3] <= LPM_DECODE:scan_sw.EQ[3]


|voltage|LPM_ROM:data_L
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => ~NO_FANOUT~
outclock => ~NO_FANOUT~
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE


|voltage|LPM_ROM:data_L|altrom:srom
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT


|voltage|LPM_ROM:data_H
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => ~NO_FANOUT~
outclock => ~NO_FANOUT~
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE


|voltage|LPM_ROM:data_H|altrom:srom
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT


|voltage|LPM_COUNTER:sw_point
clock => alt_counter_f10ke:wysi_counter.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= alt_counter_f10ke:wysi_counter.q[0]
q[1] <= alt_counter_f10ke:wysi_counter.q[1]
cout <= alt_counter_f10ke:wysi_counter.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|voltage|LPM_COUNTER:sw_point|alt_counter_f10ke:wysi_counter
data[0] => data_path[0].IN1
data[1] => data_path[1].IN1
clock => counter_cell[1].CLK
clock => counter_cell[0].CLK
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
cin => ~NO_FANOUT~
sload => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aclr => ~NO_FANOUT~
q[0] <= counter_cell[0].REGOUT
q[1] <= counter_cell[1].REGOUT
cout <= cout_bit.COMBOUT


|voltage|LPM_DECODE:scan_sw
data[0] => decode_f9c:auto_generated.data[0]
data[1] => decode_f9c:auto_generated.data[1]
enable => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
eq[0] <= decode_f9c:auto_generated.eq[0]
eq[1] <= decode_f9c:auto_generated.eq[1]
eq[2] <= decode_f9c:auto_generated.eq[2]
eq[3] <= decode_f9c:auto_generated.eq[3]


|voltage|LPM_DECODE:scan_sw|decode_f9c:auto_generated
eq[0] <= cmpr1_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= cmpr2_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= cmpr3_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= cmpr4_aeb_int.DB_MAX_OUTPUT_PORT_TYPE