voltage.map.qmsg

交流电压表相应的VHDL代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 22:05:48 2006 " "Info: Processing started: Fri Oct 27 22:05:48 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off voltage -c voltage " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off voltage -c voltage" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "voltage.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file voltage.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 voltage-main " "Info: Found design unit 1: voltage-main" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 voltage " "Info: Found entity 1: voltage" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "voltage " "Info: Elaborating entity \"voltage\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "voltage.vhd(94) " "Info: VHDL Case Statement information at voltage.vhd(94): OTHERS choice is never selected" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "LED_data voltage.vhd(98) " "Warning: VHDL Process Statement warning at voltage.vhd(98): signal or variable \"LED_data\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"LED_data\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "LPM_ROM.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM LPM_ROM:data_L " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"LPM_ROM:data_L\"" {  } { { "voltage.vhd" "data_L" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 62 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom LPM_ROM:data_L\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"LPM_ROM:data_L\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ROM LPM_ROM:data_H " "Info: Elaborating entity \"LPM_ROM\" for hierarchy \"LPM_ROM:data_H\"" {  } { { "voltage.vhd" "data_H" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 68 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom LPM_ROM:data_H\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"LPM_ROM:data_H\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "LPM_COUNTER.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_COUNTER LPM_COUNTER:sw_point " "Info: Elaborating entity \"LPM_COUNTER\" for hierarchy \"LPM_COUNTER:sw_point\"" {  } { { "voltage.vhd" "sw_point" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 77 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_counter_f10ke LPM_COUNTER:sw_point\|alt_counter_f10ke:wysi_counter " "Info: Elaborating entity \"alt_counter_f10ke\" for hierarchy \"LPM_COUNTER:sw_point\|alt_counter_f10ke:wysi_counter\"" {  } { { "LPM_COUNTER.tdf" "wysi_counter" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 404 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/LPM_DECODE.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_DECODE.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "LPM_DECODE.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_DECODE.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_DECODE LPM_DECODE:scan_sw " "Info: Elaborating entity \"LPM_DECODE\" for hierarchy \"LPM_DECODE:scan_sw\"" {  } { { "voltage.vhd" "scan_sw" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 81 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_f9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_f9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_f9c " "Info: Found entity 1: decode_f9c" {  } { { "db/decode_f9c.tdf" "" { Text "E:/yang/yl_vhdl/v1/db/decode_f9c.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_f9c LPM_DECODE:scan_sw\|decode_f9c:auto_generated " "Info: Elaborating entity \"decode_f9c\" for hierarchy \"LPM_DECODE:scan_sw\|decode_f9c:auto_generated\"" {  } { { "LPM_DECODE.tdf" "auto_generated" { Text "f:/altera/quartus50/libraries/megafunctions/LPM_DECODE.tdf" 74 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "f:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[0\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[0\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[4\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[4\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_H\|otri\[0\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_H\|otri\[0\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[1\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[1\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[5\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[5\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_H\|otri\[1\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_H\|otri\[1\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[2\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[2\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[6\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[6\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_H\|otri\[2\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_H\|otri\[2\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[3\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[3\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_L\|otri\[7\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_L\|otri\[7\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "lpm_rom:data_H\|otri\[3\] " "Warning: Removed always-enabled tri-state buffer lpm_rom:data_H\|otri\[3\] feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[0\]\$latch " "Warning: Latch LED_data\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[1\]\$latch " "Warning: Latch LED_data\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[2\]\$latch " "Warning: Latch LED_data\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[3\]\$latch " "Warning: Latch LED_data\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[4\]\$latch " "Warning: Latch LED_data\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[5\]\$latch " "Warning: Latch LED_data\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "LED_data\[6\]\$latch " "Warning: Latch LED_data\[6\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA result\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal result\[1\]" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "166 " "Info: Implemented 166 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "131 " "Info: Implemented 131 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 27 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:05:53 2006 " "Info: Processing ended: Fri Oct 27 22:05:53 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}