📄 voltage.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_8k " "Info: Detected ripple clock \"clk_8k\" as buffer" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_8k" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register x\[2\] register addr\[5\] 22.52 MHz 44.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 22.52 MHz between source register \"x\[2\]\" and destination register \"addr\[5\]\" (period= 44.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.600 ns + Longest register register " "Info: + Longest register to register delay is 18.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x\[2\] 1 REG LC3_B5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B5; Fanout = 3; REG Node = 'x\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { x[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 2.300 ns LessThan~586 2 COMB LC6_B5 1 " "Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC6_B5; Fanout = 1; COMB Node = 'LessThan~586'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "2.300 ns" { x[2] LessThan~586 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 3.800 ns LessThan~572 3 COMB LC7_B5 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 3.800 ns; Loc. = LC7_B5; Fanout = 1; COMB Node = 'LessThan~572'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "1.500 ns" { LessThan~586 LessThan~572 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 6.700 ns LessThan~556 4 COMB LC1_B5 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC1_B5; Fanout = 1; COMB Node = 'LessThan~556'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "2.900 ns" { LessThan~572 LessThan~556 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 11.200 ns LessThan~570 5 COMB LC7_B6 1 " "Info: 5: + IC(2.200 ns) + CELL(2.300 ns) = 11.200 ns; Loc. = LC7_B6; Fanout = 1; COMB Node = 'LessThan~570'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "4.500 ns" { LessThan~556 LessThan~570 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 15.200 ns addr\[0\]~8 6 COMB LC1_B7 8 " "Info: 6: + IC(2.200 ns) + CELL(1.800 ns) = 15.200 ns; Loc. = LC1_B7; Fanout = 8; COMB Node = 'addr\[0\]~8'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "4.000 ns" { LessThan~570 addr[0]~8 } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 18.600 ns addr\[5\] 7 REG LC2_B6 14 " "Info: 7: + IC(2.200 ns) + CELL(1.200 ns) = 18.600 ns; Loc. = LC2_B6; Fanout = 14; REG Node = 'addr\[5\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.400 ns" { addr[0]~8 addr[5] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.800 ns 58.06 % " "Info: Total cell delay = 10.800 ns ( 58.06 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.800 ns 41.94 % " "Info: Total interconnect delay = 7.800 ns ( 41.94 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "18.600 ns" { x[2] LessThan~586 LessThan~572 LessThan~556 LessThan~570 addr[0]~8 addr[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "18.600 ns" { x[2] LessThan~586 LessThan~572 LessThan~556 LessThan~570 addr[0]~8 addr[5] } { 0.000ns 0.600ns 0.000ns 0.600ns 2.200ns 2.200ns 2.200ns } { 0.000ns 1.700ns 1.500ns 2.300ns 2.300ns 1.800ns 1.200ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { clk } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_8k 2 REG LC1_B22 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B22; Fanout = 26; REG Node = 'clk_8k'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.600 ns" { clk clk_8k } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 12.100 ns addr\[5\] 3 REG LC2_B6 14 " "Info: 3: + IC(5.700 ns) + CELL(0.000 ns) = 12.100 ns; Loc. = LC2_B6; Fanout = 14; REG Node = 'addr\[5\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.700 ns" { clk_8k addr[5] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.23 % " "Info: Total cell delay = 3.900 ns ( 32.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 67.77 % " "Info: Total interconnect delay = 8.200 ns ( 67.77 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k addr[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k addr[5] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.100 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { clk } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_8k 2 REG LC1_B22 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B22; Fanout = 26; REG Node = 'clk_8k'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.600 ns" { clk clk_8k } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 12.100 ns x\[2\] 3 REG LC3_B5 3 " "Info: 3: + IC(5.700 ns) + CELL(0.000 ns) = 12.100 ns; Loc. = LC3_B5; Fanout = 3; REG Node = 'x\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.700 ns" { clk_8k x[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.23 % " "Info: Total cell delay = 3.900 ns ( 32.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 67.77 % " "Info: Total interconnect delay = 8.200 ns ( 67.77 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k addr[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k addr[5] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 18 -1 0 } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "18.600 ns" { x[2] LessThan~586 LessThan~572 LessThan~556 LessThan~570 addr[0]~8 addr[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "18.600 ns" { x[2] LessThan~586 LessThan~572 LessThan~556 LessThan~570 addr[0]~8 addr[5] } { 0.000ns 0.600ns 0.000ns 0.600ns 2.200ns 2.200ns 2.200ns } { 0.000ns 1.700ns 1.500ns 2.300ns 2.300ns 1.800ns 1.200ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k addr[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k addr[5] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "x\[0\] intr clk 1.100 ns register " "Info: tsu for register \"x\[0\]\" (data pin = \"intr\", clock pin = \"clk\") is 1.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.700 ns + Longest pin register " "Info: + Longest pin to register delay is 10.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns intr 1 PIN PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'intr'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { intr } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.800 ns) 6.100 ns x\[0\]~8 2 COMB LC1_C3 8 " "Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_C3; Fanout = 8; COMB Node = 'x\[0\]~8'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.300 ns" { intr x[0]~8 } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.200 ns) 10.700 ns x\[0\] 3 REG LC4_B5 2 " "Info: 3: + IC(3.400 ns) + CELL(1.200 ns) = 10.700 ns; Loc. = LC4_B5; Fanout = 2; REG Node = 'x\[0\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "4.600 ns" { x[0]~8 x[0] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 54.21 % " "Info: Total cell delay = 5.800 ns ( 54.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 45.79 % " "Info: Total interconnect delay = 4.900 ns ( 45.79 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "10.700 ns" { intr x[0]~8 x[0] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.700 ns" { intr intr~out x[0]~8 x[0] } { 0.000ns 0.000ns 1.500ns 3.400ns } { 0.000ns 2.800ns 1.800ns 1.200ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { clk } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_8k 2 REG LC1_B22 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B22; Fanout = 26; REG Node = 'clk_8k'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.600 ns" { clk clk_8k } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 12.100 ns x\[0\] 3 REG LC4_B5 2 " "Info: 3: + IC(5.700 ns) + CELL(0.000 ns) = 12.100 ns; Loc. = LC4_B5; Fanout = 2; REG Node = 'x\[0\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.700 ns" { clk_8k x[0] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.23 % " "Info: Total cell delay = 3.900 ns ( 32.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 67.77 % " "Info: Total interconnect delay = 8.200 ns ( 67.77 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[0] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[0] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "10.700 ns" { intr x[0]~8 x[0] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "10.700 ns" { intr intr~out x[0]~8 x[0] } { 0.000ns 0.000ns 1.500ns 3.400ns } { 0.000ns 2.800ns 1.800ns 1.200ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[0] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[0] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk LED_data\[5\] result\[2\] 31.300 ns register " "Info: tco from clock \"clk\" to destination pin \"LED_data\[5\]\" through register \"result\[2\]\" is 31.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { clk } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_8k 2 REG LC1_B22 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B22; Fanout = 26; REG Node = 'clk_8k'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.600 ns" { clk clk_8k } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 12.100 ns result\[2\] 3 REG LC5_A13 8 " "Info: 3: + IC(5.700 ns) + CELL(0.000 ns) = 12.100 ns; Loc. = LC5_A13; Fanout = 8; REG Node = 'result\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.700 ns" { clk_8k result[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.23 % " "Info: Total cell delay = 3.900 ns ( 32.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 67.77 % " "Info: Total interconnect delay = 8.200 ns ( 67.77 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k result[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k result[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.100 ns + Longest register pin " "Info: + Longest register to pin delay is 18.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns result\[2\] 1 REG LC5_A13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A13; Fanout = 8; REG Node = 'result\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { result[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.300 ns) 5.900 ns Mux~441 2 COMB LC1_C21 14 " "Info: 2: + IC(3.600 ns) + CELL(2.300 ns) = 5.900 ns; Loc. = LC1_C21; Fanout = 14; COMB Node = 'Mux~441'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.900 ns" { result[2] Mux~441 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.700 ns) 10.600 ns LED_data\[5\]\$latch 3 COMB LOOP LC7_C15 2 " "Info: 3: + IC(0.000 ns) + CELL(4.700 ns) = 10.600 ns; Loc. = LC7_C15; Fanout = 2; COMB LOOP Node = 'LED_data\[5\]\$latch'" { { "Info" "ITDB_PART_OF_SCC" "LED_data\[5\]\$latch LC7_C15 " "Info: Loc. = LC7_C15; Node \"LED_data\[5\]\$latch\"" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { LED_data[5]$latch } "NODE_NAME" } "" } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { LED_data[5]$latch } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "4.700 ns" { Mux~441 LED_data[5]$latch } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 18.100 ns LED_data\[5\] 4 PIN PIN_30 0 " "Info: 4: + IC(2.400 ns) + CELL(5.100 ns) = 18.100 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'LED_data\[5\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "7.500 ns" { LED_data[5]$latch LED_data[5] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns 66.85 % " "Info: Total cell delay = 12.100 ns ( 66.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 33.15 % " "Info: Total interconnect delay = 6.000 ns ( 33.15 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "18.100 ns" { result[2] Mux~441 LED_data[5]$latch LED_data[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "18.100 ns" { result[2] Mux~441 LED_data[5]$latch LED_data[5] } { 0.000ns 3.600ns 0.000ns 2.400ns } { 0.000ns 2.300ns 4.700ns 5.100ns } } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k result[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k result[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "18.100 ns" { result[2] Mux~441 LED_data[5]$latch LED_data[5] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "18.100 ns" { result[2] Mux~441 LED_data[5]$latch LED_data[5] } { 0.000ns 3.600ns 0.000ns 2.400ns } { 0.000ns 2.300ns 4.700ns 5.100ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "x\[2\] AD_data\[2\] clk 8.100 ns register " "Info: th for register \"x\[2\]\" (data pin = \"AD_data\[2\]\", clock pin = \"clk\") is 8.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 33; CLK Node = 'clk'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { clk } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_8k 2 REG LC1_B22 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B22; Fanout = 26; REG Node = 'clk_8k'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "3.600 ns" { clk clk_8k } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 12.100 ns x\[2\] 3 REG LC3_B5 3 " "Info: 3: + IC(5.700 ns) + CELL(0.000 ns) = 12.100 ns; Loc. = LC3_B5; Fanout = 3; REG Node = 'x\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.700 ns" { clk_8k x[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 32.23 % " "Info: Total cell delay = 3.900 ns ( 32.23 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns 67.77 % " "Info: Total interconnect delay = 8.200 ns ( 67.77 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" { } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns AD_data\[2\] 1 PIN PIN_1 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_1; Fanout = 1; PIN Node = 'AD_data\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "" { AD_data[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 5.600 ns x\[2\] 2 REG LC3_B5 3 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC3_B5; Fanout = 3; REG Node = 'x\[2\]'" { } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "2.800 ns" { AD_data[2] x[2] } "NODE_NAME" } "" } } { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 19 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 71.43 % " "Info: Total cell delay = 4.000 ns ( 71.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 28.57 % " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" { } { } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.600 ns" { AD_data[2] x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { AD_data[2] AD_data[2]~out x[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } } } } 0} } { { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "12.100 ns" { clk clk_8k x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "12.100 ns" { clk clk~out clk_8k x[2] } { 0.000ns 0.000ns 2.500ns 5.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" "" { Report "E:/yang/yl_vhdl/v1/db/voltage_cmp.qrpt" Compiler "voltage" "UNKNOWN" "V1" "E:/yang/yl_vhdl/v1/db/voltage.quartus_db" { Floorplan "E:/yang/yl_vhdl/v1/" "" "5.600 ns" { AD_data[2] x[2] } "NODE_NAME" } "" } } { "f:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { AD_data[2] AD_data[2]~out x[2] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 27 22:06:03 2006 " "Info: Processing ended: Fri Oct 27 22:06:03 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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