voltage.tan.qmsg

交流电压表相应的VHDL代码

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[5\]\$latch " "Info: Node \"LED_data\[5\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[4\]\$latch " "Info: Node \"LED_data\[4\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[3\]\$latch " "Info: Node \"LED_data\[3\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[2\]\$latch " "Info: Node \"LED_data\[2\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[1\]\$latch " "Info: Node \"LED_data\[1\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "LED_data\[0\]\$latch " "Info: Node \"LED_data\[0\]\$latch\"" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 98 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "voltage.vhd" "" { Text "E:/yang/yl_vhdl/v1/voltage.vhd" 8 -1 0 } } { "f:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}