📄 v1.rpt
字号:
F12 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/22( 50%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 19/141 ( 13%)
Total logic cells used: 743/1152 ( 64%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.58/4 ( 89%)
Total fan-in: 2664/4608 ( 57%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 15
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 743
Total flipflops required: 41
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 397/1152 ( 34%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 8 8 8 8 8 8 8 8 7 8 0 7 8 8 2 0 3 8 7 6 6 8 8 166/0
B: 8 0 0 2 8 8 8 0 0 8 8 7 0 8 0 6 8 8 5 8 2 8 3 6 8 127/0
C: 8 8 8 8 8 3 8 7 4 3 7 8 0 8 8 8 5 8 8 8 8 8 7 8 2 166/0
D: 8 8 8 8 8 8 8 8 8 2 7 6 0 7 0 8 0 0 0 0 0 0 0 0 0 102/0
E: 7 2 7 8 8 8 8 7 0 8 8 2 0 0 7 4 8 8 8 5 7 8 8 8 8 152/0
F: 0 8 0 8 0 0 0 0 0 0 6 8 0 0 0 0 0 0 0 0 0 0 0 0 0 30/0
Total: 39 34 31 42 40 35 40 30 20 29 43 39 0 30 23 34 23 24 24 29 24 30 24 30 26 743/0
Device-Specific Information: e:\yang\yl_vhdl\v1\v1.rpt
v1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
79 - - - -- INPUT G 0 0 0 0 cp
126 - - D -- INPUT 0 0 0 1 da0
24 - - D -- INPUT 0 0 0 1 da1
127 - - D -- INPUT 0 0 0 1 da2
26 - - D -- INPUT 0 0 0 1 da3
182 - - - -- INPUT 0 0 0 1 da4
80 - - - -- INPUT 0 0 0 1 da5
183 - - - -- INPUT 0 0 0 1 da6
184 - - - -- INPUT 0 0 0 1 da7
78 - - - -- INPUT 0 0 0 8 intr
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\yang\yl_vhdl\v1\v1.rpt
v1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
168 - - - 06 OUTPUT 0 1 0 0 ledh0
157 - - A -- OUTPUT 0 1 0 0 ledh1
149 - - A -- OUTPUT 0 1 0 0 ledh2
147 - - A -- OUTPUT 0 1 0 0 ledh3
208 - - A -- OUTPUT 0 1 0 0 rd
114 - - F -- OUTPUT 0 1 0 0 seg0
116 - - F -- OUTPUT 0 1 0 0 seg1
111 - - F -- OUTPUT 0 1 0 0 seg2
53 - - F -- OUTPUT 0 1 0 0 seg3
112 - - F -- OUTPUT 0 1 0 0 seg4
115 - - F -- OUTPUT 0 1 0 0 seg5
113 - - F -- OUTPUT 0 1 0 0 seg6
195 - - - 18 OUTPUT 0 0 0 0 uled0
71 - - - 14 OUTPUT 0 0 0 0 uled1
62 - - - 19 OUTPUT 0 0 0 0 uled2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\yang\yl_vhdl\v1\v1.rpt
v1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - D 15 AND2 0 3 0 2 |counter_600:u4|LPM_ADD_SUB:78|addcore:adder|:67
- 1 - D 15 DFFE 0 4 0 8 |counter_600:u4|rd_i (|counter_600:u4|:23)
- 4 - D 03 DFFE 2 1 0 21 |counter_600:u4|s17 (|counter_600:u4|:24)
- 6 - D 03 DFFE 2 1 0 21 |counter_600:u4|s16 (|counter_600:u4|:25)
- 2 - D 03 DFFE 2 1 0 11 |counter_600:u4|s15 (|counter_600:u4|:26)
- 3 - D 03 DFFE 2 1 0 11 |counter_600:u4|s14 (|counter_600:u4|:27)
- 1 - D 03 DFFE 2 1 0 18 |counter_600:u4|s13 (|counter_600:u4|:28)
- 8 - D 03 DFFE 2 1 0 18 |counter_600:u4|s12 (|counter_600:u4|:29)
- 5 - D 03 DFFE 2 1 0 16 |counter_600:u4|s11 (|counter_600:u4|:30)
- 7 - D 03 DFFE 2 1 0 17 |counter_600:u4|s10 (|counter_600:u4|:31)
- 7 - D 15 DFFE 0 4 0 1 |counter_600:u4|cnt4 (|counter_600:u4|:44)
- 6 - D 15 DFFE 0 3 0 2 |counter_600:u4|cnt3 (|counter_600:u4|:45)
- 3 - D 15 DFFE 0 4 0 2 |counter_600:u4|cnt2 (|counter_600:u4|:46)
- 8 - D 15 DFFE 0 3 0 4 |counter_600:u4|cnt1 (|counter_600:u4|:47)
- 1 - D 13 DFFE 0 1 0 5 |counter_600:u4|cnt0 (|counter_600:u4|:48)
- 2 - D 15 OR2 s 0 3 0 4 |counter_600:u4|~55~1
- 5 - D 15 OR2 ! 0 3 0 2 |counter_600:u4|:55
- 7 - E 04 OR2 s 0 4 0 20 |counter_600:u4|~9618~1
- 3 - D 01 OR2 ! 0 2 0 1 |counter_600:u4|:9818
- 5 - E 10 OR2 s ! 0 3 0 27 |counter_600:u4|~9878~1
- 3 - D 02 OR2 s ! 0 4 0 49 |counter_600:u4|~9978~1
- 5 - D 06 OR2 s ! 0 4 0 47 |counter_600:u4|~9998~1
- 2 - E 04 OR2 s ! 0 2 0 8 |counter_600:u4|~10018~1
- 3 - D 06 OR2 s ! 0 4 0 47 |counter_600:u4|~10018~2
- 6 - D 06 OR2 s 0 4 0 46 |counter_600:u4|~10058~1
- 6 - D 02 OR2 s ! 0 4 0 52 |counter_600:u4|~10078~1
- 7 - D 02 OR2 s ! 0 4 0 49 |counter_600:u4|~10098~1
- 1 - D 06 OR2 s ! 0 4 0 42 |counter_600:u4|~10138~1
- 4 - D 02 OR2 s 0 4 0 46 |counter_600:u4|~10158~1
- 8 - D 06 OR2 s ! 0 4 0 41 |counter_600:u4|~10178~1
- 7 - B 11 AND2 s 0 3 0 23 |counter_600:u4|~10198~1
- 1 - C 09 AND2 0 2 0 2 |counter_600:u4|:10198
- 5 - B 11 AND2 s 0 2 0 9 |counter_600:u4|~10338~1
- 7 - C 11 AND2 s 0 3 0 26 |counter_600:u4|~10578~1
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