c_20.vhd

来自「交流电压表相应的VHDL代码」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_20 is
  port(clk:in std_logic;
        co:out std_logic);
end  c_20;

architecture rtl of c_20 is
  signal s:std_logic_vector(3 downto 0);
  signal a:std_logic;
begin
  co<=a;
  process(clk)
   begin
    if(clk'event and clk='1') then
     if(s="1001") then
       s<="0000";
       a<=not a;
     else
       s<=s+1; 
     end if;
    end if;
  end process;
end  rtl;