voltage.vhd

交流电压表相应的VHDL代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library LPM;
use LPM.lpm_components.all;
entity voltage is
  port(	clk,intr		:	in std_logic;
			AD_data		:	in std_logic_vector(7 downto 0);
       	rd_wr,LED_point	: 	out std_logic;
			LED_data	:	out std_logic_vector(6 downto 0);
			sw			:	out std_logic_vector(3 downto 0)
		);
end voltage;
ARCHITECTURE main OF voltage IS
	type ram is array(0 to 3) of std_logic_vector(3 downto 0);
	SIGNAL data 				: ram;
	SIGNAL addr 				: STD_LOGIC_VECTOR(7 downto 0):="00000000";
	SIGNAL x,rom_l 				: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL rom_h,result,switch 	: STD_LOGIC_VECTOR(3 downto 0);
	SIGNAL sel 					: STD_LOGIC_VECTOR(1 downto 0);
	SIGNAL clk_8k 				: STD_LOGIC;
BEGIN
	clk_8khz:	process (clk) is
		variable n: integer;
    begin
		if clk'event and clk='1' then
			if n=1250 then
				clk_8k<= not clk_8k;
				n:=0;
			else 
				n:=n+1;
			end if;
		end if;
	end process clk_8khz;
	rd_wr<=clk_8k;
	A_to_D: process (clk_8k) is 
	begin
		if clk_8k'event and clk_8k ='0' then
			if  intr ='0' then
				x<=AD_data;
			end if;
		end if;
	end process A_to_D;
	--	addr<=x;
	addr_room: process (clk_8k)
	begin 
		if clk_8k'event and clk_8k='1' then
			if addr<x then--conv_integer(
				addr<=x;
	--	else
	--		addr<=addr;
			end if;
		end if;	
	--		addr    <= x(6 downto 0);
			data(0) <= X"E";
	--	else 
	--		addr    <= "1111111" -x(6 downto 0);
	--		data(0) <= X"F";
	--	end if;
	end process addr_room;
	data_L: component lpm_rom
		generic map (lpm_width=>8,lpm_widthad=>8,
				lpm_numwords=>256,lpm_address_control=> 
				"unregistered",lpm_file =>"E:\yang\yl_vhdl\v1\dataL.mif",
				lpm_outdata=>"unregistered")
		port map (address => addr,q => rom_l);
	data_H: component lpm_rom
		generic map (lpm_width => 4,lpm_widthad => 8,
				lpm_numwords => 256,lpm_address_control=> 
				"unregistered",lpm_file =>"E:\yang\yl_vhdl\v1\dataH.mif",
				lpm_outdata=>"unregistered")
		port map (address => addr,q => rom_h);
	data(1)	<= rom_h;
	data(2)	<= rom_l(7 downto 4);
	data(3)	<= rom_l(3 downto 0);
	sw_point: component lpm_counter
	generic map (lpm_width => 2,lpm_modulus => 4,
			lpm_direction => "up")
	port map ( clock => clk_8k,q=> sel);
scan_sw: component lpm_decode
	generic map (lpm_width => 2,lpm_decodes => 4)
	port map ( data => sel,eq=> switch);
sw <= not switch;
mux_4_to_1: process(clk_8k,sel)
begin
if clk_8k'event and clk_8k='1' then

	case sel is
		when "00"   => result <= data (3); LED_point <='0';
		when "01"   => result <= data (2); LED_point <='0';
		when "10"   => result <= data (1); LED_point <='1';
		when "11"   => result <= data (0); LED_point <='0';
		when others => null;
	end case ;
end if;
end process mux_4_to_1;
BCD_to_seg: process (result) 
begin
	case result is 
		when X"0" => LED_data <= "0111111";
		when X"1" => LED_data <= "0000110";
		when X"2" => LED_data <= "1011011";
		when X"3" => LED_data <= "1001111";
		when X"4" => LED_data <= "1100110";
		when X"5" => LED_data <= "1101101";
		when X"6" => LED_data <= "0111101";
		when X"7" => LED_data <= "0000111";
		when X"8" => LED_data <= "1111111";
		when X"9" => LED_data <= "1100111";
		when X"E" => LED_data <= "0000000";
		when X"F" => LED_data <= "1000000";
		when others => null;
	end case;
end process BCD_to_seg;
END main;