📄 voltage.rpt
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voltage
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - B -- OUTPUT 0 1 0 0 LED_data0
23 - - B -- OUTPUT 0 1 0 0 LED_data1
10 - - - 01 OUTPUT 0 1 0 0 LED_data2
25 - - B -- OUTPUT 0 1 0 0 LED_data3
24 - - B -- OUTPUT 0 1 0 0 LED_data4
37 - - - 09 OUTPUT 0 1 0 0 LED_data5
21 - - B -- OUTPUT 0 1 0 0 LED_data6
65 - - B -- OUTPUT 0 1 0 0 LED_point
60 - - C -- OUTPUT 0 1 0 0 rd_wr
66 - - B -- OUTPUT 0 1 0 0 sw0
67 - - B -- OUTPUT 0 1 0 0 sw1
64 - - B -- OUTPUT 0 1 0 0 sw2
47 - - - 14 OUTPUT 0 1 0 0 sw3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\yang\yl_vhdl\v1\voltage.rpt
voltage
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 21 AND2 0 2 0 1 |LPM_ADD_SUB:284|addcore:adder|:167
- 1 - A 21 AND2 0 4 0 4 |LPM_ADD_SUB:284|addcore:adder|:175
- 3 - A 15 AND2 0 2 0 1 |LPM_ADD_SUB:284|addcore:adder|:179
- 6 - A 23 AND2 0 4 0 4 |LPM_ADD_SUB:284|addcore:adder|:187
- 8 - A 23 AND2 0 2 0 1 |LPM_ADD_SUB:284|addcore:adder|:191
- 1 - A 23 AND2 0 4 0 2 |LPM_ADD_SUB:284|addcore:adder|:199
- 4 - A 24 AND2 0 2 0 3 |LPM_ADD_SUB:284|addcore:adder|:203
- 2 - A 22 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:211
- 4 - A 22 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:219
- 1 - A 17 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:227
- 2 - A 17 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:235
- 6 - A 14 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:243
- 1 - A 14 AND2 0 3 0 4 |LPM_ADD_SUB:284|addcore:adder|:251
- 4 - A 20 AND2 0 2 0 1 |LPM_ADD_SUB:284|addcore:adder|:255
- 3 - A 20 AND2 0 4 0 2 |LPM_ADD_SUB:284|addcore:adder|:263
- 8 - A 20 AND2 0 2 0 3 |LPM_ADD_SUB:284|addcore:adder|:267
- 3 - A 19 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:275
- 6 - A 19 AND2 0 2 0 1 |LPM_ADD_SUB:284|addcore:adder|:279
- 1 - B 14 DFFE 0 2 0 5 |LPM_COUNTER:sw_point|f8count:p8c0|QB (|LPM_COUNTER:sw_point|f8count:p8c0|:7)
- 5 - B 14 DFFE 0 1 0 6 |LPM_COUNTER:sw_point|f8count:p8c0|QA (|LPM_COUNTER:sw_point|f8count:p8c0|:8)
- 6 - B 14 OR2 ! 0 2 1 0 |LPM_DECODE:scan_sw|declut:decoder|anode3_2
- - 3 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_H|altrom:srom|segment0_0
- - 1 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_H|altrom:srom|segment0_1
- - 8 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_H|altrom:srom|segment0_2
- - 6 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_H|altrom:srom|segment0_3
- - 4 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_0
- - 8 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_1
- - 1 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_2
- - 5 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_3
- - 2 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_4
- - 7 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_5
- - 6 B -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_6
- - 2 C -- MEM_SGMT 0 8 0 1 |LPM_ROM:data_L|altrom:srom|segment0_7
- 8 - B 14 DFFE 0 3 1 0 :12
- 3 - B 14 DFFE + 0 1 1 23 clk_8k (:25)
- 1 - C 11 DFFE 2 1 0 2 x7 (:26)
- 4 - C 11 DFFE 2 1 0 2 x6 (:27)
- 2 - C 11 DFFE 2 1 0 2 x5 (:28)
- 1 - C 12 DFFE 2 1 0 2 x4 (:29)
- 3 - C 12 DFFE 2 1 0 2 x3 (:30)
- 5 - C 10 DFFE 2 1 0 2 x2 (:31)
- 6 - C 10 DFFE 2 1 0 2 x1 (:32)
- 7 - C 10 DFFE 2 1 0 2 x0 (:33)
- 5 - C 11 DFFE 0 4 0 13 addr7 (:34)
- 7 - C 11 DFFE 0 3 0 13 addr6 (:35)
- 3 - C 11 DFFE 0 3 0 13 addr5 (:36)
- 4 - C 12 DFFE 0 3 0 13 addr4 (:37)
- 8 - C 12 DFFE 0 3 0 13 addr3 (:38)
- 1 - C 10 DFFE 0 3 0 13 addr2 (:39)
- 4 - C 10 DFFE 0 3 0 13 addr1 (:40)
- 3 - C 10 DFFE 0 3 0 13 addr0 (:41)
- 3 - B 17 DFFE 0 4 0 11 result3 (:77)
- 4 - B 17 DFFE 0 4 0 11 result2 (:78)
- 2 - B 17 DFFE 0 4 0 11 result1 (:79)
- 1 - B 17 DFFE 0 4 0 12 result0 (:80)
- 7 - A 19 DFFE + 0 3 0 1 n31 (:145)
- 5 - A 19 DFFE + 0 3 0 2 n30 (:146)
- 4 - A 19 DFFE + 0 2 0 3 n29 (:147)
- 8 - A 19 DFFE + 0 3 0 2 n28 (:148)
- 8 - A 16 DFFE + 0 2 0 3 n27 (:149)
- 7 - A 20 DFFE + 0 2 0 2 n26 (:150)
- 6 - A 20 DFFE + 0 3 0 2 n25 (:151)
- 1 - A 20 DFFE + 0 3 0 3 n24 (:152)
- 2 - A 20 DFFE + 0 2 0 4 n23 (:153)
- 8 - A 14 DFFE + 0 3 0 2 n22 (:154)
- 7 - A 14 DFFE + 0 2 0 3 n21 (:155)
- 5 - A 14 DFFE + 0 3 0 2 n20 (:156)
- 3 - A 14 DFFE + 0 2 0 3 n19 (:157)
- 5 - A 17 DFFE + 0 3 0 2 n18 (:158)
- 4 - A 17 DFFE + 0 2 0 3 n17 (:159)
- 3 - A 17 DFFE + 0 3 0 2 n16 (:160)
- 8 - A 17 DFFE + 0 2 0 3 n15 (:161)
- 7 - A 22 DFFE + 0 3 0 2 n14 (:162)
- 6 - A 22 DFFE + 0 2 0 3 n13 (:163)
- 5 - A 22 DFFE + 0 3 0 2 n12 (:164)
- 8 - A 22 DFFE + 0 2 0 3 n11 (:165)
- 1 - A 24 DFFE + 0 2 0 2 n10 (:166)
- 3 - A 23 DFFE + 0 3 0 2 n9 (:167)
- 2 - A 23 DFFE + 0 3 0 3 n8 (:168)
- 7 - A 23 DFFE + 0 2 0 4 n7 (:169)
- 5 - A 23 DFFE + 0 3 0 2 n6 (:170)
- 2 - A 15 DFFE + 0 3 0 3 n5 (:171)
- 8 - A 15 DFFE + 0 2 0 4 n4 (:172)
- 7 - A 21 DFFE + 0 3 0 2 n3 (:173)
- 5 - A 21 DFFE + 0 3 0 3 n2 (:174)
- 4 - A 21 DFFE + 0 2 0 4 n1 (:175)
- 8 - A 21 DFFE + 0 1 0 5 n0 (:176)
- 4 - A 23 OR2 s 0 4 0 1 ~210~1
- 3 - A 21 OR2 s 0 4 0 1 ~210~2
- 4 - A 14 OR2 s 0 4 0 1 ~210~3
- 7 - A 17 OR2 s 0 4 0 1 ~210~4
- 1 - A 22 OR2 s 0 4 0 1 ~210~5
- 3 - A 22 OR2 s 0 4 0 1 ~210~6
- 2 - A 14 OR2 s 0 4 0 1 ~210~7
- 2 - A 19 OR2 s 0 3 0 1 ~210~8
- 5 - A 20 OR2 s 0 3 0 1 ~210~9
- 1 - A 19 OR2 s 0 4 0 1 ~210~10
- 2 - A 21 OR2 ! 0 4 0 33 :210
- 6 - C 11 OR2 0 3 0 8 :760
- 8 - C 11 OR2 ! 0 3 0 2 :765
- 2 - C 12 OR2 ! 0 3 0 1 :770
- 6 - C 12 OR2 ! 0 3 0 1 :775
- 5 - C 12 OR2 ! 0 3 0 1 :780
- 2 - C 10 OR2 ! 0 3 0 1 :785
- 8 - C 10 OR2 ! 0 4 0 1 :790
- 7 - B 14 AND2 0 2 1 4 :1246
- 4 - B 14 AND2 0 2 1 4 :1254
- 6 - B 17 OR2 0 4 0 1 :1257
- 2 - B 14 AND2 0 2 1 4 :1262
- 5 - B 17 OR2 0 4 0 1 :1274
- 7 - B 17 OR2 0 4 0 1 :1286
- 8 - B 17 OR2 0 4 0 1 :1298
- 3 - B 11 OR2 s ! 0 3 0 5 ~1636~1
- 1 - B 11 OR2 0 3 0 1 :1665
- 2 - B 03 AND2 s 0 3 0 4 ~1672~1
- 5 - B 02 AND2 0 2 0 1 :1672
- 1 - B 03 AND2 0 4 0 5 :1684
- 2 - B 11 AND2 0 4 0 3 :1696
- 6 - B 09 OR2 0 4 0 1 :1713
- 5 - B 11 AND2 s 0 3 0 1 ~1720~1
- 7 - B 03 OR2 ! 0 4 0 5 :1720
- 4 - B 03 AND2 0 4 0 3 :1732
- 3 - B 03 AND2 0 4 0 3 :1744
- 8 - B 03 OR2 s ! 0 3 0 2 ~1747~1
- 6 - B 03 OR2 ! 0 4 0 7 :1756
- 5 - B 03 AND2 0 4 0 7 :1768
- 1 - B 09 OR2 0 4 1 1 :1771
- 7 - B 09 AND2 s 0 2 0 1 ~1773~1
- 5 - B 07 AND2 s 0 1 0 2 ~1785~1
- 4 - B 09 OR2 0 3 0 1 :1786
- 5 - B 09 OR2 0 4 0 1 :1798
- 2 - B 09 OR2 0 4 1 1 :1810
- 8 - B 07 OR2 s ! 0 2 0 1 ~1812~1
- 4 - B 02 OR2 s 0 3 0 2 ~1827~1
- 7 - B 02 OR2 0 4 0 1 :1833
- 8 - B 02 OR2 0 4 0 1 :1845
- 6 - B 02 OR2 0 4 1 1 :1849
- 1 - B 02 OR2 0 4 0 1 :1864
- 3 - B 09 OR2 0 4 0 1 :1881
- 8 - B 09 OR2 0 4 1 1 :1888
- 3 - B 07 OR2 s 0 2 0 1 ~1918~1
- 1 - B 07 OR2 s 0 4 0 1 ~1918~2
- 3 - B 02 OR2 0 3 0 1 :1918
- 2 - B 02 OR2 0 4 1 1 :1927
- 1 - B 01 AND2 s 0 1 0 3 ~1945~1
- 2 - B 01 OR2 s 0 2 0 3 ~1945~2
- 7 - B 07 OR2 0 4 0 1 :1956
- 4 - B 07 OR2 0 4 1 1 :1966
- 4 - B 11 OR2 s 0 3 0 5 ~1990~1
- 6 - B 07 OR2 0 4 0 1 :1998
- 1 - B 12 OR2 s 0 2 0 5 ~1999~1
- 2 - B 07 OR2 0 4 1 1 :2005
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\yang\yl_vhdl\v1\voltage.rpt
voltage
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 26/ 48( 54%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 20/ 96( 20%) 26/ 48( 54%) 6/ 48( 12%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 7/ 96( 7%) 12/ 48( 25%) 1/ 48( 2%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\yang\yl_vhdl\v1\voltage.rpt
voltage
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 33 clk
DFF 25 clk_8k
Device-Specific Information: e:\yang\yl_vhdl\v1\voltage.rpt
voltage
** EQUATIONS **
AD_data0 : INPUT;
AD_data1 : INPUT;
AD_data2 : INPUT;
AD_data3 : INPUT;
AD_data4 : INPUT;
AD_data5 : INPUT;
AD_data6 : INPUT;
AD_data7 : INPUT;
clk : INPUT;
intr : INPUT;
-- Node name is ':41' = 'addr0'
-- Equation name is 'addr0', location is LC3_C10, type is buried.
addr0 = DFFE( _EQ001, clk_8k, VCC, VCC, VCC);
_EQ001 = addr0 & !_LC6_C11
# _LC6_C11 & x0;
-- Node name is ':40' = 'addr1'
-- Equation name is 'addr1', location is LC4_C10, type is buried.
addr1 = DFFE( _EQ002, clk_8k, VCC, VCC, VCC);
_EQ002 = addr1 & !_LC6_C11
# _LC6_C11 & x1;
-- Node name is ':39' = 'addr2'
-- Equation name is 'addr2', location is LC1_C10, type is buried.
addr2 = DFFE( _EQ003, clk_8k, VCC, VCC, VCC);
_EQ003 = addr2 & !_LC6_C11
# _LC6_C11 & x2;
-- Node name is ':38' = 'addr3'
-- Equation name is 'addr3', location is LC8_C12, type is buried.
addr3 = DFFE( _EQ004, clk_8k, VCC, VCC, VCC);
_EQ004 = addr3 & !_LC6_C11
# _LC6_C11 & x3;
-- Node name is ':37' = 'addr4'
-- Equation name is 'addr4', location is LC4_C12, type is buried.
addr4 = DFFE( _EQ005, clk_8k, VCC, VCC, VCC);
_EQ005 = addr4 & !_LC6_C11
# _LC6_C11 & x4;
-- Node name is ':36' = 'addr5'
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