voltage.map.rpt

交流电压表相应的VHDL代码

; LPM_SVALUE             ; UNUSED  ; Untyped                        ;
; DEVICE_FAMILY          ; FLEX10K ; Untyped                        ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                        ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH             ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK             ;
; CARRY_CNT_EN           ; SMART   ; Untyped                        ;
; LABWIDE_SCLR           ; ON      ; Untyped                        ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                        ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                        ;
+------------------------+---------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: LPM_DECODE:scan_sw ;
+------------------------+------------+---------------------------+
; Parameter Name         ; Value      ; Type                      ;
+------------------------+------------+---------------------------+
; LPM_WIDTH              ; 2          ; Integer                   ;
; LPM_DECODES            ; 4          ; Integer                   ;
; LPM_PIPELINE           ; 0          ; Integer                   ;
; CASCADE_CHAIN          ; MANUAL     ; Untyped                   ;
; DEVICE_FAMILY          ; FLEX10K    ; Untyped                   ;
; CBXI_PARAMETER         ; decode_f9c ; Untyped                   ;
; AUTO_CARRY_CHAINS      ; ON         ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS   ; OFF        ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS    ; ON         ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS ; OFF        ; IGNORE_CASCADE            ;
+------------------------+------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 32          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; FLEX10K     ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_soh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/yang/yl_vhdl/v1/voltage.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 27 22:05:48 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off voltage -c voltage
Info: Found 2 design units, including 1 entities, in source file voltage.vhd
    Info: Found design unit 1: voltage-main
    Info: Found entity 1: voltage
Info: Elaborating entity "voltage" for the top level hierarchy
Info: VHDL Case Statement information at voltage.vhd(94): OTHERS choice is never selected
Warning: VHDL Process Statement warning at voltage.vhd(98): signal or variable "LED_data" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "LED_data" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf
    Info: Found entity 1: lpm_rom
Info: Elaborating entity "LPM_ROM" for hierarchy "LPM_ROM:data_L"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "LPM_ROM:data_L|altrom:srom"
Info: Elaborating entity "LPM_ROM" for hierarchy "LPM_ROM:data_H"
Info: Elaborating entity "altrom" for hierarchy "LPM_ROM:data_H|altrom:srom"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "LPM_COUNTER" for hierarchy "LPM_COUNTER:sw_point"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborating entity "alt_counter_f10ke" for hierarchy "LPM_COUNTER:sw_point|alt_counter_f10ke:wysi_counter"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/LPM_DECODE.tdf
    Info: Found entity 1: lpm_decode
Info: Elaborating entity "LPM_DECODE" for hierarchy "LPM_DECODE:scan_sw"
Info: Found 1 design units, including 1 entities, in source file db/decode_f9c.tdf
    Info: Found entity 1: decode_f9c
Info: Elaborating entity "decode_f9c" for hierarchy "LPM_DECODE:scan_sw|decode_f9c:auto_generated"
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[0] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[4] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_H|otri[0] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[1] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[5] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_H|otri[1] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[2] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[6] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_H|otri[2] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[3] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_L|otri[7] feeding logic, open-drain buffer or output pin
Warning: Removed always-enabled tri-state buffer lpm_rom:data_H|otri[3] feeding logic, open-drain buffer or output pin
Warning: Latch LED_data[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Warning: Latch LED_data[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal result[1]
Info: Implemented 166 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 13 output pins
    Info: Implemented 131 logic cells
    Info: Implemented 12 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Processing ended: Fri Oct 27 22:05:53 2006
    Info: Elapsed time: 00:00:05