vgacore.map.qmsg

一个VHDL产生的VGA彩条信号程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 23 11:35:25 2007 " "Info: Processing started: Mon Apr 23 11:35:25 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vgacore -c vgacore " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vgacore -c vgacore" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgasig.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgasig.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vgasig-Behavioral " "Info: Found design unit 1: vgasig-Behavioral" {  } { { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vgasig " "Info: Found entity 1: vgasig" {  } { { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "colormap.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file colormap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 colormap-Behavioral " "Info: Found design unit 1: colormap-Behavioral" {  } { { "colormap.vhd" "" { Text "e:/yang/yl_vhdl/vga/colormap.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 colormap " "Info: Found entity 1: colormap" {  } { { "colormap.vhd" "" { Text "e:/yang/yl_vhdl/vga/colormap.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vgacore..vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vgacore..vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vgacore-Behavioral " "Info: Found design unit 1: vgacore-Behavioral" {  } { { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vgacore " "Info: Found entity 1: vgacore" {  } { { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vgacore " "Info: Elaborating entity \"vgacore\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vgasig vgasig:makesig " "Info: Elaborating entity \"vgasig\" for hierarchy \"vgasig:makesig\"" {  } { { "vgacore..vhd" "makesig" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "colormap colormap:makergb " "Info: Elaborating entity \"colormap\" for hierarchy \"colormap:makergb\"" {  } { { "vgacore..vhd" "makergb" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 90 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 8 -1 0 } } { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 9 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 23 11:35:29 2007 " "Info: Processing ended: Mon Apr 23 11:35:29 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}