vgacore.tan.qmsg

一个VHDL产生的VGA彩条信号程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 23 11:35:44 2007 " "Info: Processing started: Mon Apr 23 11:35:44 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vgacore -c vgacore " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vgacore -c vgacore" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 7 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "sysclk " "Info: Detected ripple clock \"sysclk\" as buffer" {  } { { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 19 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sysclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "vgasig:makesig\|hsyncb " "Info: Detected ripple clock \"vgasig:makesig\|hsyncb\" as buffer" {  } { { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 8 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "vgasig:makesig\|hsyncb" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk g\[1\] vgasig:makesig\|vcnt\[5\] 13.728 ns register " "Info: tco from clock \"clk\" to destination pin \"g\[1\]\" through register \"vgasig:makesig\|vcnt\[5\]\" is 13.728 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns clk 1 CLK PIN_99 1 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_99; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.298 ns) + CELL(0.809 ns) 2.815 ns sysclk 2 REG LC_X2_Y3_N2 13 " "Info: 2: + IC(1.298 ns) + CELL(0.809 ns) = 2.815 ns; Loc. = LC_X2_Y3_N2; Fanout = 13; REG Node = 'sysclk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { clk sysclk } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.718 ns) + CELL(0.809 ns) 5.342 ns vgasig:makesig\|hsyncb 3 REG LC_X3_Y3_N5 12 " "Info: 3: + IC(1.718 ns) + CELL(0.809 ns) = 5.342 ns; Loc. = LC_X3_Y3_N5; Fanout = 12; REG Node = 'vgasig:makesig\|hsyncb'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.527 ns" { sysclk vgasig:makesig|hsyncb } "NODE_NAME" } } { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.093 ns) + CELL(0.574 ns) 8.009 ns vgasig:makesig\|vcnt\[5\] 4 REG LC_X3_Y2_N5 14 " "Info: 4: + IC(2.093 ns) + CELL(0.574 ns) = 8.009 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'vgasig:makesig\|vcnt\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.667 ns" { vgasig:makesig|hsyncb vgasig:makesig|vcnt[5] } "NODE_NAME" } } { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 36.21 % ) " "Info: Total cell delay = 2.900 ns ( 36.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.109 ns ( 63.79 % ) " "Info: Total interconnect delay = 5.109 ns ( 63.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.009 ns" { clk sysclk vgasig:makesig|hsyncb vgasig:makesig|vcnt[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.009 ns" { clk clk~combout sysclk vgasig:makesig|hsyncb vgasig:makesig|vcnt[5] } { 0.000ns 0.000ns 1.298ns 1.718ns 2.093ns } { 0.000ns 0.708ns 0.809ns 0.809ns 0.574ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.484 ns + Longest register pin " "Info: + Longest register to pin delay is 5.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vgasig:makesig\|vcnt\[5\] 1 REG LC_X3_Y2_N5 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'vgasig:makesig\|vcnt\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vgasig:makesig|vcnt[5] } "NODE_NAME" } } { "vgasig.vhd" "" { Text "e:/yang/yl_vhdl/vga/vgasig.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.125 ns) 1.750 ns colormap:makergb\|Mux11~70 2 COMB LC_X2_Y1_N6 2 " "Info: 2: + IC(1.625 ns) + CELL(0.125 ns) = 1.750 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; COMB Node = 'colormap:makergb\|Mux11~70'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.750 ns" { vgasig:makesig|vcnt[5] colormap:makergb|Mux11~70 } "NODE_NAME" } } { "colormap.vhd" "" { Text "e:/yang/yl_vhdl/vga/colormap.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.431 ns) + CELL(0.571 ns) 2.752 ns rgb~2118 3 COMB LC_X2_Y1_N8 1 " "Info: 3: + IC(0.431 ns) + CELL(0.571 ns) = 2.752 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'rgb~2118'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.002 ns" { colormap:makergb|Mux11~70 rgb~2118 } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(1.454 ns) 5.484 ns g\[1\] 4 PIN PIN_16 0 " "Info: 4: + IC(1.278 ns) + CELL(1.454 ns) = 5.484 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'g\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.732 ns" { rgb~2118 g[1] } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.150 ns ( 39.20 % ) " "Info: Total cell delay = 2.150 ns ( 39.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.334 ns ( 60.80 % ) " "Info: Total interconnect delay = 3.334 ns ( 60.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.484 ns" { vgasig:makesig|vcnt[5] colormap:makergb|Mux11~70 rgb~2118 g[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.484 ns" { vgasig:makesig|vcnt[5] colormap:makergb|Mux11~70 rgb~2118 g[1] } { 0.000ns 1.625ns 0.431ns 1.278ns } { 0.000ns 0.125ns 0.571ns 1.454ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.009 ns" { clk sysclk vgasig:makesig|hsyncb vgasig:makesig|vcnt[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.009 ns" { clk clk~combout sysclk vgasig:makesig|hsyncb vgasig:makesig|vcnt[5] } { 0.000ns 0.000ns 1.298ns 1.718ns 2.093ns } { 0.000ns 0.708ns 0.809ns 0.809ns 0.574ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.484 ns" { vgasig:makesig|vcnt[5] colormap:makergb|Mux11~70 rgb~2118 g[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.484 ns" { vgasig:makesig|vcnt[5] colormap:makergb|Mux11~70 rgb~2118 g[1] } { 0.000ns 1.625ns 0.431ns 1.278ns } { 0.000ns 0.125ns 0.571ns 1.454ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "md\[1\] g\[1\] 6.652 ns Longest " "Info: Longest tpd from source pin \"md\[1\]\" to destination pin \"g\[1\]\" is 6.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns md\[1\] 1 PIN PIN_21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'md\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { md[1] } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.125 ns) 2.466 ns rgb~2108 2 COMB LC_X2_Y2_N0 8 " "Info: 2: + IC(1.633 ns) + CELL(0.125 ns) = 2.466 ns; Loc. = LC_X2_Y2_N0; Fanout = 8; COMB Node = 'rgb~2108'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.758 ns" { md[1] rgb~2108 } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.319 ns) 3.920 ns rgb~2118 3 COMB LC_X2_Y1_N8 1 " "Info: 3: + IC(1.135 ns) + CELL(0.319 ns) = 3.920 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'rgb~2118'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.454 ns" { rgb~2108 rgb~2118 } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.278 ns) + CELL(1.454 ns) 6.652 ns g\[1\] 4 PIN PIN_16 0 " "Info: 4: + IC(1.278 ns) + CELL(1.454 ns) = 6.652 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'g\[1\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.732 ns" { rgb~2118 g[1] } "NODE_NAME" } } { "vgacore..vhd" "" { Text "e:/yang/yl_vhdl/vga/vgacore..vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.606 ns ( 39.18 % ) " "Info: Total cell delay = 2.606 ns ( 39.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.046 ns ( 60.82 % ) " "Info: Total interconnect delay = 4.046 ns ( 60.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.652 ns" { md[1] rgb~2108 rgb~2118 g[1] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.652 ns" { md[1] md[1]~combout rgb~2108 rgb~2118 g[1] } { 0.000ns 0.000ns 1.633ns 1.135ns 1.278ns } { 0.000ns 0.708ns 0.125ns 0.319ns 1.454ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 23 11:35:45 2007 " "Info: Processing ended: Mon Apr 23 11:35:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}