colormap.vhd

一个VHDL产生的VGA彩条信号程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity colormap is
    Port ( hloc : in std_logic_vector(9 downto 0);
           vloc : in std_logic_vector(9 downto 0);
           rgbx : out std_logic_vector(7 downto 0);
           rgby : out std_logic_vector(7 downto 0));
end colormap;

architecture Behavioral of colormap is

begin
--然后产生彩条信号，下面是竖彩条的产生，横彩条、方格等信号产生类似。

  process(hloc,vloc)
  begin
   case hloc(7 downto 5) is
   when "000" => rgbx <=  "11111111";
   when "001" => rgbx <=  "00000000";
   when "010" => rgbx <=  "11000000";
   when "011" => rgbx <=  "00000111";
   when "100" => rgbx <=  "00111000";
   when "101" => rgbx <=  "11000111";
   when "110" => rgbx <=  "11111000";
   when "111" => rgbx <=  "11111111";
   when others => rgbx <= "00000000";
 end case;
 case vloc(7 downto 5) is
   when "000" => rgby <= "10101010";
   when "001" => rgby <= "01010101";
   when "010" => rgby <= "11001110";
   when "011" => rgby <= "00110001";
   when "100" => rgby <= "00101110";
   when "101" => rgby <= "01100110";
   when "110" => rgby <= "11111100";
   when "111" => rgby <= "00011110";
   when others => rgby <= "00000000";
  end case;
     end process;
end Behavioral;