vgasig.vhd

一个VHDL产生的VGA彩条信号程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgasig is
    Port ( clock : in std_logic;
           reset : in std_logic;
           hsyncb: buffer std_logic;
           vsyncb: out std_logic;
           enable: out std_logic;
           Xaddr : out std_logic_vector(9 downto 0);
           Yaddr : out std_logic_vector(9 downto 0));
end vgasig;

architecture Behavioral of vgasig is
--定义相关常量，可参考VGA相关工业标准
constant H_PIXELS: INTEGER:=640;
constant H_FRONT:  INTEGER:=16;
constant H_BACK:   INTEGER:=48;
constant H_SYNCTIME:INTEGER:=96;
constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRONT + H_BACK;
constant V_LINES: INTEGER:=480;
constant V_FRONT: INTEGER:=11;
constant V_BACK: INTEGER:=32;
constant V_SYNCTIME: INTEGER:=2;
constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONT + V_BACK;

signal hcnt: std_logic_vector(9 downto 0); -- 行计数器
signal vcnt: std_logic_vector(9 downto 0); -- 场计数器

begin

--产生行计数（记录每行的点数），H_PERIOD 为行周期计数值。
A: process(clock, reset)
begin
 --复位时行计数器清零
 if reset = '0' then
  hcnt <= (others => '0');
 elsif (clock'event and clock = '1') then
  --当行计数到达计数周期时将重置
  if hcnt < H_PERIOD then
   hcnt <= hcnt + 1;
  else
   hcnt <= (others => '0');
  end if;
 end if;
end process;

--产生场记数（记录每帧中的行数），V_PERIOD为场周期计数值
B: process(hsyncb, reset)
begin
 -- 复位场计数器清零
 if reset='0' then
  vcnt <= (others => '0');
 elsif (hsyncb'event and hsyncb = '1') then
   if vcnt < V_PERIOD then
   vcnt <= vcnt + 1;
  else
   vcnt <= (others => '0');
  end if;
 end if;
end process;

--产生行同步信号，H_PIXELS为行显示点数，H_FRONT为前消隐点数，H_SYNCTIME为行同步点数
C: process(clock, reset)
begin
  if reset = '0' then
  hsyncb <= '1';
 elsif (clock'event and clock = '1') then
  if (hcnt >= (H_PIXELS + H_FRONT) and hcnt < (H_PIXELS + H_SYNCTIME + H_FRONT)) then
  hsyncb <= '0';
  else
   hsyncb <= '1';
  end if;
 end if;
end process;

--产生场同步信号，V_LINES为场显示点数，V_FRONT为前消隐点数，V_SYNCTIME场同步点数
D: process(hsyncb, reset)
begin
  if reset = '0' then
  vsyncb <= '1';
  elsif (hsyncb'event and hsyncb = '1') then
  if (vcnt >= (V_LINES + V_FRONT) and vcnt < (V_LINES + V_SYNCTIME + V_FRONT)) then
   vsyncb <= '0';
  else
   vsyncb <= '1';
  end if;
 end if;
end process;

E: process (clock)
begin
 if clock'EVENT and clock = '1' then
  -- 此处enable为低
  if hcnt >= H_PIXELS or vcnt >= V_LINES then
   enable <= '0';
   else 
    enable <= '1';
   end if;
 end if;
end process;

H:
Xaddr <= hcnt;
Yaddr <= vcnt;

end Behavioral;