vgacore.tan.rpt

一个VHDL产生的VGA彩条信号程序

; N/A   ; None         ; 12.696 ns  ; vgasig:makesig|vcnt[5] ; b[2] ; clk        ;
; N/A   ; None         ; 12.463 ns  ; vgasig:makesig|vcnt[6] ; b[1] ; clk        ;
; N/A   ; None         ; 12.443 ns  ; vgasig:makesig|vcnt[6] ; b[2] ; clk        ;
; N/A   ; None         ; 12.252 ns  ; vgasig:makesig|vcnt[5] ; r[1] ; clk        ;
; N/A   ; None         ; 12.121 ns  ; vgasig:makesig|vcnt[6] ; r[1] ; clk        ;
; N/A   ; None         ; 11.944 ns  ; vgasig:makesig|vcnt[6] ; r[0] ; clk        ;
; N/A   ; None         ; 11.890 ns  ; vgasig:makesig|vcnt[7] ; r[1] ; clk        ;
; N/A   ; None         ; 11.738 ns  ; vgasig:makesig|vcnt[5] ; r[0] ; clk        ;
; N/A   ; None         ; 11.629 ns  ; vgasig:makesig|hcnt[7] ; b[0] ; clk        ;
; N/A   ; None         ; 11.583 ns  ; vgasig:makesig|hcnt[5] ; g[0] ; clk        ;
; N/A   ; None         ; 11.574 ns  ; vgasig:makesig|enable  ; b[0] ; clk        ;
; N/A   ; None         ; 11.536 ns  ; vgasig:makesig|hcnt[5] ; b[0] ; clk        ;
; N/A   ; None         ; 11.466 ns  ; vgasig:makesig|hcnt[5] ; g[1] ; clk        ;
; N/A   ; None         ; 11.431 ns  ; vgasig:makesig|hcnt[6] ; g[0] ; clk        ;
; N/A   ; None         ; 11.427 ns  ; vgasig:makesig|hcnt[6] ; b[0] ; clk        ;
; N/A   ; None         ; 11.419 ns  ; vgasig:makesig|enable  ; r[1] ; clk        ;
; N/A   ; None         ; 11.330 ns  ; vgasig:makesig|enable  ; r[0] ; clk        ;
; N/A   ; None         ; 11.314 ns  ; vgasig:makesig|hcnt[6] ; g[1] ; clk        ;
; N/A   ; None         ; 11.239 ns  ; vgasig:makesig|hcnt[7] ; g[0] ; clk        ;
; N/A   ; None         ; 11.133 ns  ; vgasig:makesig|enable  ; g[0] ; clk        ;
; N/A   ; None         ; 11.122 ns  ; vgasig:makesig|hcnt[7] ; g[1] ; clk        ;
; N/A   ; None         ; 11.012 ns  ; vgasig:makesig|enable  ; g[1] ; clk        ;
; N/A   ; None         ; 10.984 ns  ; vgasig:makesig|hcnt[5] ; r[0] ; clk        ;
; N/A   ; None         ; 10.983 ns  ; vgasig:makesig|hcnt[5] ; r[1] ; clk        ;
; N/A   ; None         ; 10.914 ns  ; vgasig:makesig|vsyncb  ; vs   ; clk        ;
; N/A   ; None         ; 10.833 ns  ; vgasig:makesig|hcnt[7] ; b[2] ; clk        ;
; N/A   ; None         ; 10.781 ns  ; vgasig:makesig|enable  ; b[2] ; clk        ;
; N/A   ; None         ; 10.740 ns  ; vgasig:makesig|hcnt[5] ; b[2] ; clk        ;
; N/A   ; None         ; 10.631 ns  ; vgasig:makesig|hcnt[6] ; b[2] ; clk        ;
; N/A   ; None         ; 10.599 ns  ; vgasig:makesig|hcnt[7] ; r[0] ; clk        ;
; N/A   ; None         ; 10.598 ns  ; vgasig:makesig|hcnt[7] ; r[1] ; clk        ;
; N/A   ; None         ; 10.584 ns  ; vgasig:makesig|hcnt[5] ; g[2] ; clk        ;
; N/A   ; None         ; 10.581 ns  ; vgasig:makesig|hcnt[7] ; b[1] ; clk        ;
; N/A   ; None         ; 10.565 ns  ; vgasig:makesig|hcnt[6] ; r[0] ; clk        ;
; N/A   ; None         ; 10.564 ns  ; vgasig:makesig|hcnt[6] ; r[1] ; clk        ;
; N/A   ; None         ; 10.528 ns  ; vgasig:makesig|enable  ; b[1] ; clk        ;
; N/A   ; None         ; 10.488 ns  ; vgasig:makesig|hcnt[5] ; b[1] ; clk        ;
; N/A   ; None         ; 10.432 ns  ; vgasig:makesig|hcnt[6] ; g[2] ; clk        ;
; N/A   ; None         ; 10.379 ns  ; vgasig:makesig|hcnt[6] ; b[1] ; clk        ;
; N/A   ; None         ; 10.240 ns  ; vgasig:makesig|hcnt[7] ; g[2] ; clk        ;
; N/A   ; None         ; 10.139 ns  ; vgasig:makesig|enable  ; g[2] ; clk        ;
; N/A   ; None         ; 8.077 ns   ; vgasig:makesig|hsyncb  ; hs   ; clk        ;
+-------+--------------+------------+------------------------+------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+-------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To   ;
+-------+-------------------+-----------------+-------+------+
; N/A   ; None              ; 6.652 ns        ; md[1] ; g[1] ;
; N/A   ; None              ; 6.630 ns        ; md[1] ; g[0] ;
; N/A   ; None              ; 6.610 ns        ; md[0] ; g[1] ;
; N/A   ; None              ; 6.588 ns        ; md[0] ; g[0] ;
; N/A   ; None              ; 6.541 ns        ; md[1] ; b[0] ;
; N/A   ; None              ; 6.499 ns        ; md[0] ; b[0] ;
; N/A   ; None              ; 6.280 ns        ; md[0] ; r[1] ;
; N/A   ; None              ; 6.191 ns        ; md[0] ; r[0] ;
; N/A   ; None              ; 6.054 ns        ; md[1] ; r[1] ;
; N/A   ; None              ; 5.965 ns        ; md[1] ; r[0] ;
; N/A   ; None              ; 5.868 ns        ; md[1] ; b[1] ;
; N/A   ; None              ; 5.864 ns        ; md[1] ; b[2] ;
; N/A   ; None              ; 5.826 ns        ; md[0] ; b[1] ;
; N/A   ; None              ; 5.822 ns        ; md[0] ; b[2] ;
; N/A   ; None              ; 5.771 ns        ; md[1] ; g[2] ;
; N/A   ; None              ; 5.729 ns        ; md[0] ; g[2] ;
+-------+-------------------+-----------------+-------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Apr 23 11:35:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vgacore -c vgacore
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "sysclk" as buffer
    Info: Detected ripple clock "vgasig:makesig|hsyncb" as buffer
Info: tco from clock "clk" to destination pin "g[1]" through register "vgasig:makesig|vcnt[5]" is 13.728 ns
    Info: + Longest clock path from clock "clk" to source register is 8.009 ns
        Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_99; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.298 ns) + CELL(0.809 ns) = 2.815 ns; Loc. = LC_X2_Y3_N2; Fanout = 13; REG Node = 'sysclk'
        Info: 3: + IC(1.718 ns) + CELL(0.809 ns) = 5.342 ns; Loc. = LC_X3_Y3_N5; Fanout = 12; REG Node = 'vgasig:makesig|hsyncb'
        Info: 4: + IC(2.093 ns) + CELL(0.574 ns) = 8.009 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'vgasig:makesig|vcnt[5]'
        Info: Total cell delay = 2.900 ns ( 36.21 % )
        Info: Total interconnect delay = 5.109 ns ( 63.79 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Longest register to pin delay is 5.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N5; Fanout = 14; REG Node = 'vgasig:makesig|vcnt[5]'
        Info: 2: + IC(1.625 ns) + CELL(0.125 ns) = 1.750 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; COMB Node = 'colormap:makergb|Mux11~70'
        Info: 3: + IC(0.431 ns) + CELL(0.571 ns) = 2.752 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'rgb~2118'
        Info: 4: + IC(1.278 ns) + CELL(1.454 ns) = 5.484 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'g[1]'
        Info: Total cell delay = 2.150 ns ( 39.20 % )
        Info: Total interconnect delay = 3.334 ns ( 60.80 % )
Info: Longest tpd from source pin "md[1]" to destination pin "g[1]" is 6.652 ns
    Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'md[1]'
    Info: 2: + IC(1.633 ns) + CELL(0.125 ns) = 2.466 ns; Loc. = LC_X2_Y2_N0; Fanout = 8; COMB Node = 'rgb~2108'
    Info: 3: + IC(1.135 ns) + CELL(0.319 ns) = 3.920 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'rgb~2118'
    Info: 4: + IC(1.278 ns) + CELL(1.454 ns) = 6.652 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'g[1]'
    Info: Total cell delay = 2.606 ns ( 39.18 % )
    Info: Total interconnect delay = 4.046 ns ( 60.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Apr 23 11:35:45 2007
    Info: Elapsed time: 00:00:02