led.map.eqn

VERILOG实现LED的控制

-- Copyright (C) 1991-2006 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
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--count[1] is count[1]
count[1]_p1_out = rst & !count[1] & count[0];
count[1]_or_out = count[1]_p1_out;
count[1]_reg_input = count[1]_or_out;
count[1] = DFFE(count[1]_reg_input, GLOBAL(clk), , , );


--count[0] is count[0]
count[0]_p1_out = rst & !count[1] & !count[0];
count[0]_or_out = count[0]_p1_out;
count[0]_reg_input = count[0]_or_out;
count[0] = DFFE(count[0]_reg_input, GLOBAL(clk), , , );


--A1L15 is disp_dat.0001~26
A1L15_p1_out = !count[1] & count[0];
A1L15_p2_out = !A1L15 & count[1] & count[0];
A1L15_p3_out = !A1L15 & !count[1] & count[0];
A1L15_or_out = A1L15_p1_out # A1L15_p2_out # A1L15_p3_out # GND;
A1L15 = !(A1L15_or_out);


--A1L17 is disp_dat.0010~24
A1L17_p2_out = count[1] & !A1L17 & count[0];
A1L17_p3_out = count[1] & !A1L17;
A1L17_p4_out = count[1] & !count[0];
A1L17_or_out = GND # A1L17_p2_out # A1L17_p3_out # A1L17_p4_out;
A1L17 = !(A1L17_or_out);


--A1L14 is disp_dat.0000~24
A1L14_p1_out = !count[1] & !count[0];
A1L14_p2_out = A1L14 & count[1] & count[0];
A1L14_p3_out = A1L14 & !count[1] & !count[0];
A1L14_p4_out = !count[1] & !count[0];
A1L14_or_out = A1L14_p1_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;
A1L14 = A1L14_or_out;


--A1L5 is c1$latch~10
A1L5_p1_out = A1L3 & A1L2;
A1L5_p2_out = A1L5 & count[1] & count[0];
A1L5_p3_out = A1L5 & A1L3;
A1L5_or_out = A1L5_p1_out # A1L5_p2_out # A1L5_p3_out;
A1L5 = A1L5_or_out;


--A1L7 is c2$latch~10
A1L7_p1_out = A1L1 & A1L2;
A1L7_p2_out = A1L7 & count[1] & count[0];
A1L7_p3_out = A1L7 & A1L1;
A1L7_or_out = A1L7_p1_out # A1L7_p2_out # A1L7_p3_out;
A1L7 = A1L7_or_out;


--A1L9 is c3$latch~10
A1L9_p1_out = !count[1] & A1L2;
A1L9_p2_out = count[1] & A1L9 & count[0];
A1L9_p3_out = !count[1] & A1L9;
A1L9_or_out = A1L9_p1_out # A1L9_p2_out # A1L9_p3_out;
A1L9 = A1L9_or_out;


--A1L18 is reduce_or~4
A1L18_p1_out = A1L15 & !A1L14;
A1L18_or_out = A1L18_p1_out;
A1L18 = A1L18_or_out;


--A1L19 is reduce_or~6
A1L19_p1_out = A1L15 & A1L17;
A1L19_or_out = A1L19_p1_out;
A1L19 = A1L19_or_out;


--A1L20 is reduce_or~8
A1L20_p1_out = A1L17 & !A1L14;
A1L20_or_out = A1L20_p1_out;
A1L20 = !(A1L20_or_out);


--A1L16 is disp_dat.0001~29
A1L16_or_out = A1L15;
A1L16 = A1L16_or_out;


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--A1L3 is Decoder~37sexp
A1L3 = EXP(!count[1] & !count[0]);


--A1L1 is Decoder~34sexp
A1L1 = EXP(!count[1] & count[0]);


--A1L2 is Decoder~35sexp
A1L2 = EXP(count[1] & count[0]);


--clk is clk
--operation mode is input

clk = INPUT();


--rst is rst
--operation mode is input

rst = INPUT();


--seg[0] is seg[0]
--operation mode is output

seg[0] = OUTPUT(~GND~0);


--seg[2] is seg[2]
--operation mode is output

seg[2] = OUTPUT(~VCC~0);


--seg[3] is seg[3]
--operation mode is output

seg[3] = OUTPUT(A1L17);


--seg[4] is seg[4]
--operation mode is output

seg[4] = OUTPUT(A1L15);


--c1 is c1
--operation mode is output

c1 = OUTPUT(A1L5);


--c2 is c2
--operation mode is output

c2 = OUTPUT(A1L7);


--c3 is c3
--operation mode is output

c3 = OUTPUT(A1L9);


--seg[1] is seg[1]
--operation mode is output

seg[1] = OUTPUT(A1L16);


--seg[5] is seg[5]
--operation mode is output

seg[5] = OUTPUT(A1L20);


--seg[6] is seg[6]
--operation mode is output

seg[6] = OUTPUT(A1L19);


--seg[7] is seg[7]
--operation mode is output

seg[7] = OUTPUT(A1L18);