led.tan.qmsg

VERILOG实现LED的控制

{ "Info" "ITDB_TSU_RESULT" "count\[1\] rst clk 6.900 ns register " "Info: tsu for register \"count\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is 6.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns + Longest pin register " "Info: + Longest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns rst 1 PIN PIN_81 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 2; PIN Node = 'rst'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { rst } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.800 ns) 7.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "6.000 ns" { rst count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 55.56 % ) " "Info: Total cell delay = 4.000 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 44.44 % ) " "Info: Total interconnect delay = 3.200 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.200 ns" { rst count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { rst rst~out count[1] } { 0.000ns 0.000ns 3.200ns } { 0.000ns 1.200ns 2.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk 1 CLK PIN_125 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { clk } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "0.800 ns" { clk count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.200 ns" { rst count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { rst rst~out count[1] } { 0.000ns 0.000ns 3.200ns } { 0.000ns 1.200ns 2.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg\[7\] count\[1\] 20.900 ns register " "Info: tco from clock \"clk\" to destination pin \"seg\[7\]\" through register \"count\[1\]\" is 20.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk 1 CLK PIN_125 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { clk } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "0.800 ns" { clk count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.100 ns + Longest register pin " "Info: + Longest register to pin delay is 16.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC1 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.200 ns) 7.200 ns disp_dat.0001~26 2 COMB LOOP LC3 6 " "Info: 2: + IC(0.000 ns) + CELL(7.200 ns) = 7.200 ns; Loc. = LC3; Fanout = 6; COMB LOOP Node = 'disp_dat.0001~26'" { { "Info" "ITDB_PART_OF_SCC" "disp_dat.0001~26 LC3 " "Info: Loc. = LC3; Node \"disp_dat.0001~26\"" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { disp_dat.0001~26 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { disp_dat.0001~26 } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.200 ns" { count[1] disp_dat.0001~26 } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 14.500 ns reduce_or~4 3 COMB LC11 1 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 14.500 ns; Loc. = LC11; Fanout = 1; COMB Node = 'reduce_or~4'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.300 ns" { disp_dat.0001~26 reduce_or~4 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 16.100 ns seg\[7\] 4 PIN PIN_142 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 16.100 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'seg\[7\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "1.600 ns" { reduce_or~4 seg[7] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.800 ns ( 79.50 % ) " "Info: Total cell delay = 12.800 ns ( 79.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 20.50 % ) " "Info: Total interconnect delay = 3.300 ns ( 20.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "16.100 ns" { count[1] disp_dat.0001~26 reduce_or~4 seg[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "16.100 ns" { count[1] disp_dat.0001~26 reduce_or~4 seg[7] } { 0.000ns 0.000ns 3.300ns 0.000ns } { 0.000ns 7.200ns 4.000ns 1.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "16.100 ns" { count[1] disp_dat.0001~26 reduce_or~4 seg[7] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "16.100 ns" { count[1] disp_dat.0001~26 reduce_or~4 seg[7] } { 0.000ns 0.000ns 3.300ns 0.000ns } { 0.000ns 7.200ns 4.000ns 1.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "count\[1\] rst clk -2.800 ns register " "Info: th for register \"count\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is -2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk 1 CLK PIN_125 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { clk } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "0.800 ns" { clk count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.200 ns + " "Info: + Micro hold delay of destination is 1.200 ns" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns rst 1 PIN PIN_81 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 2; PIN Node = 'rst'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { rst } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.800 ns) 7.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "6.000 ns" { rst count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 55.56 % ) " "Info: Total cell delay = 4.000 ns ( 55.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 44.44 % ) " "Info: Total interconnect delay = 3.200 ns ( 44.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.200 ns" { rst count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { rst rst~out count[1] } { 0.000ns 0.000ns 3.200ns } { 0.000ns 1.200ns 2.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "7.200 ns" { rst count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "7.200 ns" { rst rst~out count[1] } { 0.000ns 0.000ns 3.200ns } { 0.000ns 1.200ns 2.800ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 19:53:26 2008 " "Info: Processing ended: Wed Apr 23 19:53:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}