led.tan.qmsg

VERILOG实现LED的控制

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "c2\$latch~10 " "Info: Node \"c2\$latch~10\"" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 25 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 25 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "c1\$latch~10 " "Info: Node \"c1\$latch~10\"" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 25 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 25 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_dat.0000~24 " "Info: Node \"disp_dat.0000~24\"" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_dat.0010~24 " "Info: Node \"disp_dat.0010~24\"" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "disp_dat.0001~26 " "Info: Node \"disp_dat.0001~26\"" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } } { "e:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register count\[0\] 95.24 MHz 10.5 ns Internal " "Info: Clock \"clk\" has Internal fmax of 95.24 MHz between source register \"count\[1\]\" and destination register \"count\[0\]\" (period= 10.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LC1 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(2.800 ns) 6.000 ns count\[0\] 2 REG LC2 23 " "Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 6.000 ns; Loc. = LC2; Fanout = 23; REG Node = 'count\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "6.000 ns" { count[1] count[0] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 46.67 % ) " "Info: Total cell delay = 2.800 ns ( 46.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 53.33 % ) " "Info: Total interconnect delay = 3.200 ns ( 53.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "6.000 ns" { count[1] count[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "6.000 ns" { count[1] count[0] } { 0.000ns 3.200ns } { 0.000ns 2.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk 1 CLK PIN_125 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { clk } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns count\[0\] 2 REG LC2 23 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC2; Fanout = 23; REG Node = 'count\[0\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "0.800 ns" { clk count[0] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.200 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns clk 1 CLK PIN_125 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "" { clk } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.200 ns count\[1\] 2 REG LC1 26 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count\[1\]'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "0.800 ns" { clk count[1] } "NODE_NAME" } "" } } { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 100.00 % ) " "Info: Total cell delay = 3.200 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "6.000 ns" { count[1] count[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "6.000 ns" { count[1] count[0] } { 0.000ns 3.200ns } { 0.000ns 2.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[0] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "led" "UNKNOWN" "V1" "F:/工程教育/CPLD/第一步led/db/led.quartus_db" { Floorplan "F:/工程教育/CPLD/第一步led/" "" "3.200 ns" { clk count[1] } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.200 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.400ns 0.800ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}