led.map.qmsg

VERILOG实现LED的控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 23 19:53:19 2008 " "Info: Processing started: Wed Apr 23 19:53:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led -c led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led.v" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led " "Info: Elaborating entity \"led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "led.v(25) " "Warning (10270): Verilog HDL statement warning at led.v(25): incomplete Case Statement has no default case item" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 25 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c1 led.v(23) " "Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable \"c1\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"c1\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 23 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c2 led.v(23) " "Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable \"c2\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"c2\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 23 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "c3 led.v(23) " "Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable \"c3\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"c3\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 23 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "disp_dat led.v(23) " "Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable \"disp_dat\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"disp_dat\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 23 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.1000 " "Warning: LATCH primitive \"disp_dat.1000\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.0111 " "Warning: LATCH primitive \"disp_dat.0111\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.0110 " "Warning: LATCH primitive \"disp_dat.0110\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.0101 " "Warning: LATCH primitive \"disp_dat.0101\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.0100 " "Warning: LATCH primitive \"disp_dat.0100\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "disp_dat.0011 " "Warning: LATCH primitive \"disp_dat.0011\" is permanently disabled" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 6 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[0\] GND " "Warning: Pin \"seg\[0\]\" stuck at GND" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 4 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[2\] VCC " "Warning: Pin \"seg\[2\]\" stuck at VCC" {  } { { "led.v" "" { Text "F:/工程教育/CPLD/第一步led/led.v" 4 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "30 " "Info: Implemented 30 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "14 " "Info: Implemented 14 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "3 " "Info: Implemented 3 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 23 19:53:20 2008 " "Info: Processing ended: Wed Apr 23 19:53:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}