led.v

VERILOG实现LED的控制

module led(clk,rst,seg,c1,c2,c3);
input rst;
input clk;
output [7:0] seg;                             //数码管段控制信号
output c1,c2,c3;                              //LED数码管选择
reg [3:0] disp_dat;
reg [7:0] reg_seg; 
reg [1:0] count;
reg c1,c2,c3;

always @ (posedge clk)
begin
if(rst==1'b0)
 begin
 count<=2'b00;
 end 
else
 begin
  if(count==2'b10) count<=2'b00;
  else count<=count+2'b01;               //数码管选择信号控制
 end
end
always @(count)
begin
case(count)
   2'b00: 
     begin 
       c1<=1'b0;
       c2<=1'b1;
       c3<=1'b1;
       disp_dat<=4'b0000;
     end                                 //数码管1
   2'b01:
     begin
       c1<=1'b1;
       c2<=1'b0;
       c3<=1'b1;
       disp_dat<=4'b0001;
     end                                  //数码管2
    2'b10:
     begin 
       c1<=1'b1;
       c2<=1'b1;
       c3<=1'b0;
       disp_dat<=4'b0010;
     end                                  //数码管3
  endcase
end
/*************译码电路****************/
always @(disp_dat)
begin
  case(disp_dat)
     4'b0000:  reg_seg<=8'b01111110;
     4'b0001:  reg_seg<=8'b00001100;
     4'b0010:  reg_seg<=8'b10110110;
     4'b0011:  reg_seg<=8'b10011110;
     4'b0100:  reg_seg<=8'b11001100;
     4'b0101:  reg_seg<=8'b11011010;
     4'b0110:  reg_seg<=8'b11111010;
     4'b0111:  reg_seg<=8'b00001110;
     4'b1000:  reg_seg<=8'b11111110;
     4'b1001:  reg_seg<=8'b11011110;
  endcase
end
/*************译码电路****************/
  
assign seg=reg_seg;
endmodule