📄 led.fit.rpt
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+-----------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+--------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL ; 10 pF ; Not Available ;
; LVCMOS ; 10 pF ; Not Available ;
; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
; 2.5 V ; 10 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+----------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |led ; 14 ; 17 ; |led ;
+----------------------------+------------+------+---------------------+
+--------------------------------------------------------------------------------------+
; Control Signals ;
+------+----------+---------+-------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+-------+--------+----------------------+------------------+
; clk ; PIN_125 ; 2 ; Clock ; yes ; On ; -- ;
+------+----------+---------+-------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk ; PIN_125 ; 2 ; On ; -- ;
+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+------------------+--------------+
; Name ; Fan-Out ;
+------------------+--------------+
; count[0] ; 11 ;
; count[1] ; 11 ;
; disp_dat.0001~26 ; 5 ;
; disp_dat.0010~24 ; 4 ;
; Decoder~35sexp ; 3 ;
; disp_dat.0000~24 ; 3 ;
; rst ; 2 ;
; c3$latch~10 ; 2 ;
; c2$latch~10 ; 2 ;
; c1$latch~10 ; 2 ;
; Decoder~34sexp ; 1 ;
; Decoder~37sexp ; 1 ;
; ~VCC~0 ; 1 ;
; ~GND~0 ; 1 ;
; disp_dat.0001~29 ; 1 ;
; reduce_or~8 ; 1 ;
; reduce_or~6 ; 1 ;
; reduce_or~4 ; 1 ;
+------------------+--------------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 11 / 576 ( 2 % ) ;
; PIAs ; 11 / 576 ( 2 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 0.69) ; Number of LABs (Total = 2) ;
+----------------------------------------------+-----------------------------+
; 0 ; 14 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 0.88) ; Number of LABs (Total = 2) ;
+----------------------------------------+-----------------------------+
; 0 ; 14 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+----------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 0.19) ; Number of LABs (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 15 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC1 ; clk, rst, count[1], count[0] ; disp_dat.0010~24, c3$latch~10, count[0], disp_dat.0000~24, Decoder~37sexp, count[1], disp_dat.0001~26, Decoder~34sexp, Decoder~35sexp, c1$latch~10, c2$latch~10 ;
; A ; LC2 ; clk, rst, count[1], count[0] ; count[0], disp_dat.0000~24, Decoder~37sexp, count[1], disp_dat.0001~26, Decoder~34sexp, Decoder~35sexp, disp_dat.0010~24, c1$latch~10, c2$latch~10, c3$latch~10 ;
; A ; LC3 ; disp_dat.0001~26, count[1], count[0] ; disp_dat.0001~26, reduce_or~4, reduce_or~6, seg[4], disp_dat.0001~29 ;
; A ; LC5 ; count[1], disp_dat.0010~24, count[0] ; disp_dat.0010~24, reduce_or~6, reduce_or~8, seg[3] ;
; A ; LC4 ; disp_dat.0000~24, count[1], count[0] ; disp_dat.0000~24, reduce_or~4, reduce_or~8 ;
; A ; LC16 ; c1$latch~10, Decoder~37sexp, Decoder~35sexp, count[1], count[0] ; c1$latch~10, c1 ;
; A ; LC14 ; c2$latch~10, Decoder~34sexp, Decoder~35sexp, count[1], count[0] ; c2$latch~10, c2 ;
; A ; LC13 ; count[1], c3$latch~10, Decoder~35sexp, count[0] ; c3$latch~10, c3 ;
; A ; LC11 ; disp_dat.0001~26, disp_dat.0000~24 ; seg[7] ;
; A ; LC6 ; disp_dat.0010~24, disp_dat.0000~24 ; seg[5] ;
; B ; LC25 ; disp_dat.0001~26, disp_dat.0010~24 ; seg[6] ;
; B ; LC24 ; disp_dat.0001~26 ; seg[1] ;
; B ; LC21 ; ; seg[0] ;
; B ; LC19 ; ; seg[2] ;
+-----+------------+-----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Wed Apr 23 19:53:22 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led -c led
Info: Selected device EPM3256ATC144-10 for design "led"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Apr 23 19:53:22 2008
Info: Elapsed time: 00:00:01
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