led.tan.rpt

VERILOG实现LED的控制

; N/A   ; None         ; 20.900 ns  ; count[0] ; seg[7] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[1] ; seg[6] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[0] ; seg[6] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[1] ; seg[5] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[0] ; seg[5] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[1] ; seg[1] ; clk        ;
; N/A   ; None         ; 20.900 ns  ; count[0] ; seg[1] ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[1] ; c3     ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[0] ; c3     ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[1] ; c2     ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[0] ; c2     ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[1] ; c1     ; clk        ;
; N/A   ; None         ; 17.300 ns  ; count[0] ; c1     ; clk        ;
; N/A   ; None         ; 13.600 ns  ; count[1] ; seg[4] ; clk        ;
; N/A   ; None         ; 13.600 ns  ; count[0] ; seg[4] ; clk        ;
; N/A   ; None         ; 13.600 ns  ; count[1] ; seg[3] ; clk        ;
; N/A   ; None         ; 13.600 ns  ; count[0] ; seg[3] ; clk        ;
+-------+--------------+------------+----------+--------+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.800 ns ; rst  ; count[1] ; clk      ;
; N/A           ; None        ; -2.800 ns ; rst  ; count[0] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Apr 23 19:53:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Found combinational loop of 1 nodes
    Info: Node "c3$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "c2$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "c1$latch~10"
Info: Found combinational loop of 1 nodes
    Info: Node "disp_dat.0000~24"
Info: Found combinational loop of 1 nodes
    Info: Node "disp_dat.0010~24"
Info: Found combinational loop of 1 nodes
    Info: Node "disp_dat.0001~26"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 95.24 MHz between source register "count[1]" and destination register "count[0]" (period= 10.5 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 6.000 ns; Loc. = LC2; Fanout = 23; REG Node = 'count[0]'
        Info: Total cell delay = 2.800 ns ( 46.67 % )
        Info: Total interconnect delay = 3.200 ns ( 53.33 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC2; Fanout = 23; REG Node = 'count[0]'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.200 ns
            Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
            Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tsu for register "count[1]" (data pin = "rst", clock pin = "clk") is 6.900 ns
    Info: + Longest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 2; PIN Node = 'rst'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "seg[7]" through register "count[1]" is 20.900 ns
    Info: + Longest clock path from clock "clk" to source register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 16.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: 2: + IC(0.000 ns) + CELL(7.200 ns) = 7.200 ns; Loc. = LC3; Fanout = 6; COMB LOOP Node = 'disp_dat.0001~26'
            Info: Loc. = LC3; Node "disp_dat.0001~26"
        Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 14.500 ns; Loc. = LC11; Fanout = 1; COMB Node = 'reduce_or~4'
        Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 16.100 ns; Loc. = PIN_142; Fanout = 0; PIN Node = 'seg[7]'
        Info: Total cell delay = 12.800 ns ( 79.50 % )
        Info: Total interconnect delay = 3.300 ns ( 20.50 % )
Info: th for register "count[1]" (data pin = "rst", clock pin = "clk") is -2.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.200 ns
        Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_125; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: Total cell delay = 3.200 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.200 ns
    Info: - Shortest pin to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_81; Fanout = 2; PIN Node = 'rst'
        Info: 2: + IC(3.200 ns) + CELL(2.800 ns) = 7.200 ns; Loc. = LC1; Fanout = 26; REG Node = 'count[1]'
        Info: Total cell delay = 4.000 ns ( 55.56 % )
        Info: Total interconnect delay = 3.200 ns ( 44.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Apr 23 19:53:26 2008
    Info: Elapsed time: 00:00:01