📄 led.map.rpt
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Analysis & Synthesis report for led
Wed Apr 23 19:53:20 2008
Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Apr 23 19:53:20 2008 ;
; Quartus II Version ; 5.1 Build 216 03/06/2006 SP 2 SJ Full Version ;
; Revision Name ; led ;
; Top-level Entity Name ; led ;
; Family ; MAX3000A ;
; Total macrocells ; 14 ;
; Total pins ; 13 ;
+-----------------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+------------------+---------------+
; Device ; EPM3256ATC144-10 ; ;
; Top-level entity name ; led ; led ;
; Family name ; MAX3000A ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
+----------------------------------------------------------------------+------------------+---------------+
+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+----------------------------------+
; led.v ; yes ; User Verilog HDL File ; F:/工程教育/CPLD/第一步led/led.v ;
+----------------------------------+-----------------+------------------------+----------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 14 ;
; Total registers ; 2 ;
; I/O pins ; 13 ;
; Shareable expanders ; 3 ;
; Maximum fan-out node ; count[1] ;
; Maximum fan-out ; 11 ;
; Total fan-out ; 55 ;
; Average fan-out ; 1.83 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |led ; 14 ; 13 ; |led ;
+----------------------------+------------+------+---------------------+
+---------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+---+
; Latch Name ; ;
+-----------------------------------------------+---+
; disp_dat.0001 ; ;
; disp_dat.0010 ; ;
; disp_dat.0000 ; ;
; c1$latch ; ;
; c2$latch ; ;
; c3$latch ; ;
; Number of user-specified and inferred latches ; 6 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/工程教育/CPLD/第一步led/led.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Wed Apr 23 19:53:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led
Info: Found 1 design units, including 1 entities, in source file led.v
Info: Found entity 1: led
Info: Elaborating entity "led" for the top level hierarchy
Warning (10270): Verilog HDL statement warning at led.v(25): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable "c1" may not be assigned a new value in every possible path through the Always Construct. Variable "c1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable "c2" may not be assigned a new value in every possible path through the Always Construct. Variable "c2" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable "c3" may not be assigned a new value in every possible path through the Always Construct. Variable "c3" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at led.v(23): variable "disp_dat" may not be assigned a new value in every possible path through the Always Construct. Variable "disp_dat" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: LATCH primitive "disp_dat.1000" is permanently disabled
Warning: LATCH primitive "disp_dat.0111" is permanently disabled
Warning: LATCH primitive "disp_dat.0110" is permanently disabled
Warning: LATCH primitive "disp_dat.0101" is permanently disabled
Warning: LATCH primitive "disp_dat.0100" is permanently disabled
Warning: LATCH primitive "disp_dat.0011" is permanently disabled
Warning: Output pins are stuck at VCC or GND
Warning: Pin "seg[0]" stuck at GND
Warning: Pin "seg[2]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 30 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 11 output pins
Info: Implemented 14 macrocells
Info: Implemented 3 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Wed Apr 23 19:53:20 2008
Info: Elapsed time: 00:00:01
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