led.fit.eqn

VERILOG实现LED的控制

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--count[1] is count[1] at LC1
count[1]_p1_out = rst & !count[1] & count[0];
count[1]_or_out = count[1]_p1_out;
count[1]_reg_input = count[1]_or_out;
count[1] = DFFE(count[1]_reg_input, GLOBAL(clk), , , );


--count[0] is count[0] at LC2
count[0]_p1_out = rst & !count[1] & !count[0];
count[0]_or_out = count[0]_p1_out;
count[0]_reg_input = count[0]_or_out;
count[0] = DFFE(count[0]_reg_input, GLOBAL(clk), , , );


--A1L19 is disp_dat.0001~26 at LC3
A1L19_p1_out = !count[1] & count[0];
A1L19_p2_out = !A1L19 & count[1] & count[0];
A1L19_p3_out = !A1L19 & !count[1] & count[0];
A1L19_or_out = A1L19_p1_out # A1L19_p2_out # A1L19_p3_out # GND;
A1L19 = !(A1L19_or_out);


--A1L21 is disp_dat.0010~24 at LC5
A1L21_p2_out = count[1] & !A1L21 & count[0];
A1L21_p3_out = count[1] & !A1L21;
A1L21_p4_out = count[1] & !count[0];
A1L21_or_out = GND # A1L21_p2_out # A1L21_p3_out # A1L21_p4_out;
A1L21 = !(A1L21_or_out);


--A1L18 is disp_dat.0000~24 at LC4
A1L18_p1_out = !count[1] & !count[0];
A1L18_p2_out = A1L18 & count[1] & count[0];
A1L18_p3_out = A1L18 & !count[1] & !count[0];
A1L18_p4_out = !count[1] & !count[0];
A1L18_or_out = A1L18_p1_out # A1L18_p2_out # A1L18_p3_out # A1L18_p4_out;
A1L18 = A1L18_or_out;


--A1L9 is c1$latch~10 at LC16
A1L9_p1_out = A1L3 & A1L2;
A1L9_p2_out = A1L9 & count[1] & count[0];
A1L9_p3_out = A1L9 & A1L3;
A1L9_or_out = A1L9_p1_out # A1L9_p2_out # A1L9_p3_out;
A1L9 = A1L9_or_out;


--A1L11 is c2$latch~10 at LC14
A1L11_p1_out = A1L1 & A1L2;
A1L11_p2_out = A1L11 & count[1] & count[0];
A1L11_p3_out = A1L11 & A1L1;
A1L11_or_out = A1L11_p1_out # A1L11_p2_out # A1L11_p3_out;
A1L11 = A1L11_or_out;


--A1L13 is c3$latch~10 at LC13
A1L13_p1_out = !count[1] & A1L2;
A1L13_p2_out = count[1] & A1L13 & count[0];
A1L13_p3_out = !count[1] & A1L13;
A1L13_or_out = A1L13_p1_out # A1L13_p2_out # A1L13_p3_out;
A1L13 = A1L13_or_out;


--A1L22 is reduce_or~4 at LC11
A1L22_p1_out = A1L19 & !A1L18;
A1L22_or_out = A1L22_p1_out;
A1L22 = A1L22_or_out;


--A1L23 is reduce_or~6 at LC25
A1L23_p1_out = A1L19 & A1L21;
A1L23_or_out = A1L23_p1_out;
A1L23 = A1L23_or_out;


--A1L24 is reduce_or~8 at LC6
A1L24_p1_out = A1L21 & !A1L18;
A1L24_or_out = A1L24_p1_out;
A1L24 = !(A1L24_or_out);


--A1L20 is disp_dat.0001~29 at LC24
A1L20_or_out = A1L19;
A1L20 = A1L20_or_out;


--~GND~0 is ~GND~0 at LC21
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--~VCC~0 is ~VCC~0 at LC19
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--A1L3 is Decoder~37sexp at SEXP3
A1L3 = EXP(!count[1] & !count[0]);


--A1L1 is Decoder~34sexp at SEXP2
A1L1 = EXP(!count[1] & count[0]);


--A1L2 is Decoder~35sexp at SEXP1
A1L2 = EXP(count[1] & count[0]);


--clk is clk at PIN_125
--operation mode is input

clk = INPUT();


--rst is rst at PIN_81
--operation mode is input

rst = INPUT();


--seg[0] is seg[0] at PIN_9
--operation mode is output

seg[0] = OUTPUT(~GND~0);


--seg[2] is seg[2] at PIN_10
--operation mode is output

seg[2] = OUTPUT(~VCC~0);


--seg[3] is seg[3] at PIN_1
--operation mode is output

seg[3] = OUTPUT(A1L21);


--seg[4] is seg[4] at PIN_2
--operation mode is output

seg[4] = OUTPUT(A1L19);


--c1 is c1 at PIN_139
--operation mode is output

c1 = OUTPUT(A1L9);


--c2 is c2 at PIN_140
--operation mode is output

c2 = OUTPUT(A1L11);


--c3 is c3 at PIN_141
--operation mode is output

c3 = OUTPUT(A1L13);


--seg[1] is seg[1] at PIN_8
--operation mode is output

seg[1] = OUTPUT(A1L20);


--seg[5] is seg[5] at PIN_143
--operation mode is output

seg[5] = OUTPUT(A1L24);


--seg[6] is seg[6] at PIN_7
--operation mode is output

seg[6] = OUTPUT(A1L23);


--seg[7] is seg[7] at PIN_142
--operation mode is output

seg[7] = OUTPUT(A1L22);