yl_cic32.vhd

一个三阶梳妆滤波器（CIC）的vhdl的源码

--*************************************************
--*     CIC（考虑计算剪除） 滤波器VHDL语言程序    *
--* VERSION 1.0 COPYRIGHT (A) BY  杨亮  2006.06.03*
--*      大规模器件类型 EP1S40                    *
--*           主频 40MHz                          *
--*************************************************
--Input bit width  Bin=20
--Outpur bit winth Bout=20
--级数：S＝3
--微分因子:R=16
--延时因子:D=2
--最小不混迭位数为:Bmax=39


--**************库定义、包定义********************
--package n_bit_int is              --用户自定义
--	subtype word30 is integer range  0 to 2**35-1;---2**34
--	subtype word31 is integer range  -2**30-1 to 2**30-1;---2**30
--	subtype word29 is integer range  -2**28-1 to 2**28-1;---2**26
--	subtype word28 is integer range  -2**27-1 to 2**27-1;---2**25
--	subtype word27 is integer range  -2**26-1 to 2**26-1;---2**24
--	subtype word25 is integer range  -2**24-1 to 2**24-1;---2**23
--end n_bit_int;

--library work;
--use work.n_bit_int.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--******************实体定义***********************
ENTITY  yl_cic32   IS
	port(	clk		: 	in	std_logic;						--主频输入
			x_in	:	in	std_logic_vector(23 downto 0);	--输入序列
			y_out	:	out	std_logic_vector(23 downto 0)	--输出序列
		 );
end yl_cic32;		
--******************构造体定义*********************
ARCHITECTURE  flex  OF yl_cic32  IS
 type 	state_type is (hold,sample);			--自定义枚举型				
 signal state	:	state_type;					--定义为枚举型
 signal	count	:	integer range 0 to 7;--15;			--计数变量
 signal clk2	:	std_logic;						--
 signal x		:	std_logic_vector(23 downto 0);
 signal sxtx	:	std_logic_vector(38 downto 0);	--信号扩展
 signal i0		:	std_logic_vector(38 downto 0);							--			
 signal i1		:	std_logic_vector(38 downto 0);--std_logic_vector(34 downto 0);							--	
 signal i2		:	std_logic_vector(38 downto 0);							--word31;
 signal i2d1,i2d2,c1,c0 : std_logic_vector(38 downto 0);--word29;
 signal c1d1,c1d2,c2 : std_logic_vector(38 downto 0);--word28;
 signal c2d1,c2d2,c3 : std_logic_vector(38 downto 0);--word27;
begin
 FSM:PROCESS(clk)
 begin
	--wait until clk='0';
	if(clk='0')then
	case state is
		when hold=>
			 if(count<7)then
				state<=hold;
			 else
				state<=sample;
			 end if;
		when others=>state<=hold;
	end case;
	end if;
 END PROCESS FSM;
--****************符号扩展进程***************
 Sxt:PROCESS(x)
 begin
	sxtx(23 downto 0)<=x;
	for k in 38 downto 24 loop
	 sxtx(k)<=x(x'high);
	end loop;
END PROCESS Sxt;
--****************积分器和梳状部分的时钟分频进程***************
 Int:PROCESS(clk)
 begin
 --wait until clk='1';
	if(clk='1')then
	x<=x_in;
	i0<=i0+sxtx;
	i1<=i1+i0;--(38 downto 4);
	i2<=i2+i1;--conv_integer(i1(34 downto 4));
	case state is
		when sample=>
				c0<=i2;
				count<=0;
		when others=>
				count<=count+1;
	end case;
	if(count>2 and count<4)then
		clk2<='1';
	else
		clk2<='0';
	end if;
	end if;
 END PROCESS Int;
--*****************梳状滤波器进程**************
 comb:process(clk2)
 begin
	if(clk2='1')then
		i2d1<=c0;
		i2d2<=i2d1;
		c1	<=c0-i2d2;
		c1d1<=c1;--/2;
		c1d2<=c1d1;
		c2	<=c1-c1d2;--/2-c1d2;
		c2d1<=c2;--/2;
		c2d2<=c2d1;
		c3	<=c2-c2d2;--/2-c2d2;
	end if;
 end process comb;
 y_out<=c3(38 downto 15);--conv_std_logic_vector(c3/8,24);
end flex;