counter60.sim.rpt

VHDL硬件描述

The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                         ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+
; Node Name                                                     ; Output Port Name                                              ; Output Port Type ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+
; |Counter60|Temp_Q2~4                                          ; |Counter60|Temp_Q2~4                                          ; out              ;
; |Counter60|Temp_Q2[3]                                         ; |Counter60|Temp_Q2[3]                                         ; regout           ;
; |Counter60|Q2[3]                                              ; |Counter60|Q2[3]                                              ; pin_out          ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0     ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0     ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~1                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~1                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~2                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~2                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1     ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1     ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[2]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[2]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[1]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[1]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; |Counter60|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~4                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~4                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~5                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~5                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~6                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~6                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~7                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~7                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~10                ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~10                ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~13                ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~13                ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~1                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~1                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~2                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~2                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1     ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1     ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~4                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~4                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~5                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~5                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~6                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~6                 ; out0             ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                         ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+
; Node Name                                                     ; Output Port Name                                              ; Output Port Type ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+
; |Counter60|Temp_Q2~4                                          ; |Counter60|Temp_Q2~4                                          ; out              ;
; |Counter60|Temp_Q2[3]                                         ; |Counter60|Temp_Q2[3]                                         ; regout           ;
; |Counter60|Q2[3]                                              ; |Counter60|Q2[3]                                              ; pin_out          ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0     ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]~0     ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[0]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~1                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~1                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~2                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~2                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1     ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]~1     ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[3]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[2]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[2]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[1]       ; |Counter60|lpm_add_sub:Add1|addcore:adder|datab_node[1]       ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; |Counter60|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~1 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~4                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~4                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~5                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~5                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~6                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~6                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~7                 ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~7                 ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~10                ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~10                ; out0             ;
; |Counter60|lpm_add_sub:Add1|addcore:adder|_~13                ; |Counter60|lpm_add_sub:Add1|addcore:adder|_~13                ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0     ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[0]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~1                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~1                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~2                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~2                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1     ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1     ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[3]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[2]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; |Counter60|lpm_add_sub:Add0|addcore:adder|datab_node[1]       ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~4                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~4                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~5                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~5                 ; out0             ;
; |Counter60|lpm_add_sub:Add0|addcore:adder|_~6                 ; |Counter60|lpm_add_sub:Add0|addcore:adder|_~6                 ; out0             ;
+---------------------------------------------------------------+---------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 12 17:40:02 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Counter60 -c Counter60
Info: Using vector source file "D:/altera/61/quartus/bin/Home_Work/Counter60/Counter60.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      76.80 %
Info: Number of transitions in simulation is 9510
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 84 megabytes of memory during processing
    Info: Processing ended: Sat Apr 12 17:40:03 2008
    Info: Elapsed time: 00:00:01