counter60.tan.rpt

VHDL硬件描述

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2]    ; Temp_Q1[3]    ; CLK        ; CLK      ; None                        ; None                      ; 0.894 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2]    ; Temp_Q1[0]    ; CLK        ; CLK      ; None                        ; None                      ; 0.891 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2]    ; Temp_Q1[2]    ; CLK        ; CLK      ; None                        ; None                      ; 0.885 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1]    ; Temp_Q1[1]    ; CLK        ; CLK      ; None                        ; None                      ; 0.855 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+--------+---------------+----------+
; Slack ; Required tsu ; Actual tsu ; From   ; To            ; To Clock ;
+-------+--------------+------------+--------+---------------+----------+
; N/A   ; None         ; 8.600 ns   ; Enable ; Temp_Q2[0]    ; CLK      ;
; N/A   ; None         ; 8.600 ns   ; Enable ; Temp_Q2[2]    ; CLK      ;
; N/A   ; None         ; 8.600 ns   ; Enable ; Temp_Q2[1]    ; CLK      ;
; N/A   ; None         ; 7.573 ns   ; Enable ; Temp_Q1[0]    ; CLK      ;
; N/A   ; None         ; 7.573 ns   ; Enable ; Temp_Q1[2]    ; CLK      ;
; N/A   ; None         ; 7.573 ns   ; Enable ; Temp_Q1[1]    ; CLK      ;
; N/A   ; None         ; 7.573 ns   ; Enable ; Temp_Q1[3]    ; CLK      ;
; N/A   ; None         ; 7.378 ns   ; Enable ; Out_High~reg0 ; CLK      ;
+-------+--------------+------------+--------+---------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 10.751 ns  ; Out_High~reg0 ; Out_High ; CLK        ;
; N/A   ; None         ; 6.897 ns   ; Temp_Q2[2]    ; Q2[2]    ; CLK        ;
; N/A   ; None         ; 6.880 ns   ; Temp_Q1[0]    ; Q1[0]    ; CLK        ;
; N/A   ; None         ; 6.879 ns   ; Temp_Q2[1]    ; Q2[1]    ; CLK        ;
; N/A   ; None         ; 6.874 ns   ; Temp_Q2[0]    ; Q2[0]    ; CLK        ;
; N/A   ; None         ; 6.725 ns   ; Temp_Q1[3]    ; Q1[3]    ; CLK        ;
; N/A   ; None         ; 6.458 ns   ; Temp_Q1[1]    ; Q1[1]    ; CLK        ;
; N/A   ; None         ; 6.447 ns   ; Temp_Q1[2]    ; Q1[2]    ; CLK        ;
+-------+--------------+------------+---------------+----------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+--------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To            ; To Clock ;
+---------------+-------------+-----------+--------+---------------+----------+
; N/A           ; None        ; -7.326 ns ; Enable ; Out_High~reg0 ; CLK      ;
; N/A           ; None        ; -7.521 ns ; Enable ; Temp_Q1[0]    ; CLK      ;
; N/A           ; None        ; -7.521 ns ; Enable ; Temp_Q1[2]    ; CLK      ;
; N/A           ; None        ; -7.521 ns ; Enable ; Temp_Q1[1]    ; CLK      ;
; N/A           ; None        ; -7.521 ns ; Enable ; Temp_Q1[3]    ; CLK      ;
; N/A           ; None        ; -8.548 ns ; Enable ; Temp_Q2[0]    ; CLK      ;
; N/A           ; None        ; -8.548 ns ; Enable ; Temp_Q2[2]    ; CLK      ;
; N/A           ; None        ; -8.548 ns ; Enable ; Temp_Q2[1]    ; CLK      ;
+---------------+-------------+-----------+--------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sat Apr 19 21:59:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Counter60 -c Counter60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "Temp_Q1[3]" and destination register "Temp_Q2[0]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.801 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y16_N2; Fanout = 6; REG Node = 'Temp_Q1[3]'
            Info: 2: + IC(0.564 ns) + CELL(0.590 ns) = 1.154 ns; Loc. = LC_X1_Y16_N7; Fanout = 2; COMB Node = 'LessThan0~52'
            Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.450 ns; Loc. = LC_X1_Y16_N8; Fanout = 3; COMB Node = 'Temp_Q2[0]~272'
            Info: 4: + IC(0.484 ns) + CELL(0.867 ns) = 2.801 ns; Loc. = LC_X1_Y16_N1; Fanout = 5; REG Node = 'Temp_Q2[0]'
            Info: Total cell delay = 1.571 ns ( 56.09 % )
            Info: Total interconnect delay = 1.230 ns ( 43.91 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N1; Fanout = 5; REG Node = 'Temp_Q2[0]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N2; Fanout = 6; REG Node = 'Temp_Q1[3]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "Temp_Q2[0]" (data pin = "Enable", clock pin = "CLK") is 8.600 ns
    Info: + Longest pin to register delay is 11.517 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_169; Fanout = 6; PIN Node = 'Enable'
        Info: 2: + IC(8.107 ns) + CELL(0.590 ns) = 10.166 ns; Loc. = LC_X1_Y16_N8; Fanout = 3; COMB Node = 'Temp_Q2[0]~272'
        Info: 3: + IC(0.484 ns) + CELL(0.867 ns) = 11.517 ns; Loc. = LC_X1_Y16_N1; Fanout = 5; REG Node = 'Temp_Q2[0]'
        Info: Total cell delay = 2.926 ns ( 25.41 % )
        Info: Total interconnect delay = 8.591 ns ( 74.59 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y16_N1; Fanout = 5; REG Node = 'Temp_Q2[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "CLK" to destination pin "Out_High" through register "Out_High~reg0" is 10.751 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y16_N2; Fanout = 2; REG Node = 'Out_High~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.573 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y16_N2; Fanout = 2; REG Node = 'Out_High~reg0'
        Info: 2: + IC(5.449 ns) + CELL(2.124 ns) = 7.573 ns; Loc. = PIN_137; Fanout = 0; PIN Node = 'Out_High'
        Info: Total cell delay = 2.124 ns ( 28.05 % )
        Info: Total interconnect delay = 5.449 ns ( 71.95 % )
Info: th for register "Out_High~reg0" (data pin = "Enable", clock pin = "CLK") is -7.326 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y16_N2; Fanout = 2; REG Node = 'Out_High~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 10.295 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_169; Fanout = 6; PIN Node = 'Enable'
        Info: 2: + IC(8.088 ns) + CELL(0.738 ns) = 10.295 ns; Loc. = LC_X2_Y16_N2; Fanout = 2; REG Node = 'Out_High~reg0'
        Info: Total cell delay = 2.207 ns ( 21.44 % )
        Info: Total interconnect delay = 8.088 ns ( 78.56 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 99 megabytes of memory during processing
    Info: Processing ended: Sat Apr 19 21:59:00 2008
    Info: Elapsed time: 00:00:00