📄 counter60.tan.rpt
字号:
Classic Timing Analyzer report for Counter60
Sat Apr 19 21:59:01 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 8.600 ns ; Enable ; Temp_Q2[1] ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 10.751 ns ; Out_High~reg0 ; Out_High ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -7.326 ns ; Enable ; Out_High~reg0 ; -- ; CLK ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q2[1] ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 2.801 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 2.801 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 2.801 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 2.625 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 2.625 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 2.625 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[2] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.573 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 2.537 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 2.537 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 2.537 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.426 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[1] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.364 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 2.340 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 2.340 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 2.340 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.250 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.162 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[0] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 2.079 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[2] ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 1.965 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q1[2] ; CLK ; CLK ; None ; None ; 1.741 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q1[0] ; CLK ; CLK ; None ; None ; 1.738 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q1[3] ; CLK ; CLK ; None ; None ; 1.734 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[0] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 1.333 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[0] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 1.330 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q1[2] ; CLK ; CLK ; None ; None ; 1.328 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q1[3] ; CLK ; CLK ; None ; None ; 1.328 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q1[0] ; CLK ; CLK ; None ; None ; 1.327 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[0] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 1.324 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q1[2] ; CLK ; CLK ; None ; None ; 1.307 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q1[0] ; CLK ; CLK ; None ; None ; 1.305 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[1] ; Temp_Q1[3] ; CLK ; CLK ; None ; None ; 1.301 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[3] ; Temp_Q1[1] ; CLK ; CLK ; None ; None ; 1.299 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[1] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 1.151 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[1] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 1.150 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[1] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 1.150 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q1[0] ; Temp_Q1[1] ; CLK ; CLK ; None ; None ; 1.078 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Out_High~reg0 ; Out_High~reg0 ; CLK ; CLK ; None ; None ; 1.014 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[2] ; Temp_Q2[0] ; CLK ; CLK ; None ; None ; 0.910 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[2] ; Temp_Q2[1] ; CLK ; CLK ; None ; None ; 0.907 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Temp_Q2[2] ; Temp_Q2[2] ; CLK ; CLK ; None ; None ; 0.897 ns ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -