📄 counter.sim.rpt
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; |Counter|Q1[2] ; |Counter|Q1[2] ; regout ;
; |Counter|Q1[3] ; |Counter|Q1[3] ; regout ;
; |Counter|Out_High~reg0 ; |Counter|Out_High~reg0 ; regout ;
; |Counter|Reset ; |Counter|Reset ; out ;
; |Counter|Enable ; |Counter|Enable ; out ;
; |Counter|CLK ; |Counter|CLK ; out ;
; |Counter|Out_High ; |Counter|Out_High ; pin_out ;
; |Counter|Q[0] ; |Counter|Q[0] ; pin_out ;
; |Counter|Q[1] ; |Counter|Q[1] ; pin_out ;
; |Counter|Q[2] ; |Counter|Q[2] ; pin_out ;
; |Counter|Q[3] ; |Counter|Q[3] ; pin_out ;
; |Counter|LessThan0~16 ; |Counter|LessThan0~16 ; out0 ;
; |Counter|LessThan0~17 ; |Counter|LessThan0~17 ; out0 ;
; |Counter|LessThan0~18 ; |Counter|LessThan0~18 ; out0 ;
; |Counter|LessThan0~19 ; |Counter|LessThan0~19 ; out0 ;
; |Counter|LessThan0~20 ; |Counter|LessThan0~20 ; out0 ;
; |Counter|LessThan0~21 ; |Counter|LessThan0~21 ; out0 ;
; |Counter|lpm_add_sub:Add0|result_node[0] ; |Counter|lpm_add_sub:Add0|result_node[0] ; out0 ;
; |Counter|lpm_add_sub:Add0|result_node[1] ; |Counter|lpm_add_sub:Add0|result_node[1] ; out0 ;
; |Counter|lpm_add_sub:Add0|result_node[2] ; |Counter|lpm_add_sub:Add0|result_node[2] ; out0 ;
; |Counter|lpm_add_sub:Add0|result_node[3] ; |Counter|lpm_add_sub:Add0|result_node[3] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~0 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~0 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~3 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~3 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; |Counter|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~7 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~8 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~8 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~9 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~9 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~10 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~10 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~11 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~11 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~12 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~12 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~13 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~13 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~14 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~14 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~15 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~15 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |Counter|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout ;
+------------------------------------------------------------------------------+------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~1 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~2 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~4 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~5 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~6 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~1 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~2 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |Counter|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~4 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~5 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |Counter|lpm_add_sub:Add0|addcore:adder|_~6 ; |Counter|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
+---------------------------------------------------------+---------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sat Apr 12 17:14:18 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Counter -c Counter
Info: Using vector source file "D:/altera/61/quartus/bin/Home_Work/Counter/Counter.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 83.08 %
Info: Number of transitions in simulation is 7725
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 84 megabytes of memory during processing
Info: Processing ended: Sat Apr 12 17:14:19 2008
Info: Elapsed time: 00:00:01
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