box.hier_info

正弦波 发生器,VHDL的应用和处理,可以产生任意波形

|BOX
CLK => CLK_COUNT_400HZ[18].CLK
CLK => CLK_COUNT_400HZ[17].CLK
CLK => CLK_COUNT_400HZ[16].CLK
CLK => CLK_COUNT_400HZ[15].CLK
CLK => CLK_COUNT_400HZ[14].CLK
CLK => CLK_COUNT_400HZ[13].CLK
CLK => CLK_COUNT_400HZ[12].CLK
CLK => CLK_COUNT_400HZ[11].CLK
CLK => CLK_COUNT_400HZ[10].CLK
CLK => CLK_COUNT_400HZ[9].CLK
CLK => CLK_COUNT_400HZ[8].CLK
CLK => CLK_COUNT_400HZ[7].CLK
CLK => CLK_COUNT_400HZ[6].CLK
CLK => CLK_COUNT_400HZ[5].CLK
CLK => CLK_COUNT_400HZ[4].CLK
CLK => CLK_COUNT_400HZ[3].CLK
CLK => CLK_COUNT_400HZ[2].CLK
CLK => CLK_COUNT_400HZ[1].CLK
CLK => CLK_COUNT_400HZ[0].CLK
CLK => CLK_400HZ.CLK
CLK => PLLU:u2.inclk0
CLK => CLK_COUNT_400HZ[19].CLK
RES => CLK_COUNT_400HZ~20.OUTPUTSELECT
RES => CLK_COUNT_400HZ~21.OUTPUTSELECT
RES => CLK_COUNT_400HZ~22.OUTPUTSELECT
RES => CLK_COUNT_400HZ~23.OUTPUTSELECT
RES => CLK_COUNT_400HZ~24.OUTPUTSELECT
RES => CLK_COUNT_400HZ~25.OUTPUTSELECT
RES => CLK_COUNT_400HZ~26.OUTPUTSELECT
RES => CLK_COUNT_400HZ~27.OUTPUTSELECT
RES => CLK_COUNT_400HZ~28.OUTPUTSELECT
RES => CLK_COUNT_400HZ~29.OUTPUTSELECT
RES => CLK_COUNT_400HZ~30.OUTPUTSELECT
RES => CLK_COUNT_400HZ~31.OUTPUTSELECT
RES => CLK_COUNT_400HZ~32.OUTPUTSELECT
RES => CLK_COUNT_400HZ~33.OUTPUTSELECT
RES => CLK_COUNT_400HZ~34.OUTPUTSELECT
RES => CLK_COUNT_400HZ~35.OUTPUTSELECT
RES => CLK_COUNT_400HZ~36.OUTPUTSELECT
RES => CLK_COUNT_400HZ~37.OUTPUTSELECT
RES => CLK_COUNT_400HZ~38.OUTPUTSELECT
RES => CLK_COUNT_400HZ~39.OUTPUTSELECT
RES => CLK_400HZ~1.OUTPUTSELECT
RES => DATA_BUS_VALUE[7].ACLR
RES => DATA_BUS_VALUE[6].ACLR
RES => DATA_BUS_VALUE[5].PRESET
RES => DATA_BUS_VALUE[4].PRESET
RES => DATA_BUS_VALUE[3].PRESET
RES => DATA_BUS_VALUE[2].ACLR
RES => DATA_BUS_VALUE[1].ACLR
RES => DATA_BUS_VALUE[0].ACLR
RES => LCD_E~reg0.PRESET
RES => LCD_RS~reg0.ACLR
RES => LCD_RW~reg0.ACLR
RES => PLLU:u2.areset
RES => state~113.IN1
RES => next_command~115.IN1
DOUT[0] <= allwave:u1.q[0]
DOUT[1] <= allwave:u1.q[1]
DOUT[2] <= allwave:u1.q[2]
DOUT[3] <= allwave:u1.q[3]
DOUT[4] <= allwave:u1.q[4]
DOUT[5] <= allwave:u1.q[5]
DOUT[6] <= allwave:u1.q[6]
DOUT[7] <= allwave:u1.q[7]
DS0 => process1~1.IN0
DS0 => process1~3.IN0
DS0 => process1~0.IN0
DS0 => process1~2.IN0
LCD_RS <= LCD_RS~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA_BUS[0] <= DATA_BUS~15
DATA_BUS[1] <= DATA_BUS~14
DATA_BUS[2] <= DATA_BUS~13
DATA_BUS[3] <= DATA_BUS~12
DATA_BUS[4] <= DATA_BUS~11
DATA_BUS[5] <= DATA_BUS~10
DATA_BUS[6] <= DATA_BUS~9
DATA_BUS[7] <= DATA_BUS~8
DS1 => process1~2.IN1
DS1 => process1~3.IN1
DS1 => process1~0.IN1
DS1 => process1~1.IN1


|BOX|allwave:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|BOX|allwave:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_dpu:auto_generated.address_a[0]
address_a[1] => altsyncram_dpu:auto_generated.address_a[1]
address_a[2] => altsyncram_dpu:auto_generated.address_a[2]
address_a[3] => altsyncram_dpu:auto_generated.address_a[3]
address_a[4] => altsyncram_dpu:auto_generated.address_a[4]
address_a[5] => altsyncram_dpu:auto_generated.address_a[5]
address_a[6] => altsyncram_dpu:auto_generated.address_a[6]
address_a[7] => altsyncram_dpu:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_dpu:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_dpu:auto_generated.q_a[0]
q_a[1] <= altsyncram_dpu:auto_generated.q_a[1]
q_a[2] <= altsyncram_dpu:auto_generated.q_a[2]
q_a[3] <= altsyncram_dpu:auto_generated.q_a[3]
q_a[4] <= altsyncram_dpu:auto_generated.q_a[4]
q_a[5] <= altsyncram_dpu:auto_generated.q_a[5]
q_a[6] <= altsyncram_dpu:auto_generated.q_a[6]
q_a[7] <= altsyncram_dpu:auto_generated.q_a[7]
q_b[0] <= <GND>


|BOX|allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated
address_a[0] => altsyncram_sfa2:altsyncram1.address_a[0]
address_a[1] => altsyncram_sfa2:altsyncram1.address_a[1]
address_a[2] => altsyncram_sfa2:altsyncram1.address_a[2]
address_a[3] => altsyncram_sfa2:altsyncram1.address_a[3]
address_a[4] => altsyncram_sfa2:altsyncram1.address_a[4]
address_a[5] => altsyncram_sfa2:altsyncram1.address_a[5]
address_a[6] => altsyncram_sfa2:altsyncram1.address_a[6]
address_a[7] => altsyncram_sfa2:altsyncram1.address_a[7]
clock0 => altsyncram_sfa2:altsyncram1.clock0
q_a[0] <= altsyncram_sfa2:altsyncram1.q_a[0]
q_a[1] <= altsyncram_sfa2:altsyncram1.q_a[1]
q_a[2] <= altsyncram_sfa2:altsyncram1.q_a[2]
q_a[3] <= altsyncram_sfa2:altsyncram1.q_a[3]
q_a[4] <= altsyncram_sfa2:altsyncram1.q_a[4]
q_a[5] <= altsyncram_sfa2:altsyncram1.q_a[5]
q_a[6] <= altsyncram_sfa2:altsyncram1.q_a[6]
q_a[7] <= altsyncram_sfa2:altsyncram1.q_a[7]


|BOX|allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5
address_b[5] => ram_block3a1.PORTBADDR5
address_b[5] => ram_block3a2.PORTBADDR5
address_b[5] => ram_block3a3.PORTBADDR5
address_b[5] => ram_block3a4.PORTBADDR5
address_b[5] => ram_block3a5.PORTBADDR5
address_b[5] => ram_block3a6.PORTBADDR5
address_b[5] => ram_block3a7.PORTBADDR5
address_b[6] => ram_block3a0.PORTBADDR6
address_b[6] => ram_block3a1.PORTBADDR6
address_b[6] => ram_block3a2.PORTBADDR6
address_b[6] => ram_block3a3.PORTBADDR6
address_b[6] => ram_block3a4.PORTBADDR6
address_b[6] => ram_block3a5.PORTBADDR6
address_b[6] => ram_block3a6.PORTBADDR6
address_b[6] => ram_block3a7.PORTBADDR6
address_b[7] => ram_block3a0.PORTBADDR7
address_b[7] => ram_block3a1.PORTBADDR7
address_b[7] => ram_block3a2.PORTBADDR7
address_b[7] => ram_block3a3.PORTBADDR7
address_b[7] => ram_block3a4.PORTBADDR7
address_b[7] => ram_block3a5.PORTBADDR7
address_b[7] => ram_block3a6.PORTBADDR7
address_b[7] => ram_block3a7.PORTBADDR7
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1