box.map.eqn

正弦波 发生器,VHDL的应用和处理,可以产生任意波形

--HB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]
--operation mode is normal

HB1_state[12] = AMPP_FUNCTION(A1L5, HB1_state[11], HB1_state[10], VCC, !A1L7);


--HB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
--operation mode is normal

HB1_state[2] = AMPP_FUNCTION(A1L5, HB1_state[8], HB1_state[1], HB1_state[15], VCC, !A1L7);


--C1L32 is sld_hub:sld_hub_inst|jtag_debug_mode~171
--operation mode is normal

C1L32 = AMPP_FUNCTION(HB1_state[12], A1L7, HB1_state[2]);


--HB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]
--operation mode is normal

HB1_state[15] = AMPP_FUNCTION(A1L5, HB1_state[12], HB1_state[14], VCC, !A1L7);


--HB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]
--operation mode is normal

HB1_state[0] = AMPP_FUNCTION(A1L5, A1L7, HB1_state[9], HB1L19, HB1_state[0], VCC);


--FB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8]
--operation mode is normal

FB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, C1_CLRN_SIGNAL, HB1_state[4], C1L27);


--C1L23 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21
--operation mode is normal

C1L23 = AMPP_FUNCTION(A1L7, HB1_state[4], C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q);


--M5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]
--operation mode is normal

M5_dffs[1] = AMPP_FUNCTION(A1L5, M5_dffs[2], HB1_state[0], HB1_state[11]);


--M5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
--operation mode is normal

M5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, HB1_state[0], HB1_state[11]);


--M5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
--operation mode is normal

M5_dffs[8] = AMPP_FUNCTION(A1L5, M5_dffs[9], HB1_state[0], HB1_state[11]);


--M5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]
--operation mode is normal

M5_dffs[7] = AMPP_FUNCTION(A1L5, M5_dffs[8], HB1_state[0], HB1_state[11]);


--M5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]
--operation mode is normal

M5_dffs[6] = AMPP_FUNCTION(A1L5, M5_dffs[7], HB1_state[0], HB1_state[11]);


--C1L6 is sld_hub:sld_hub_inst|Equal~182
--operation mode is normal

C1L6 = AMPP_FUNCTION(M5_dffs[9], M5_dffs[8], M5_dffs[7], M5_dffs[6]);


--M5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]
--operation mode is normal

M5_dffs[3] = AMPP_FUNCTION(A1L5, M5_dffs[4], HB1_state[0], HB1_state[11]);


--M5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]
--operation mode is normal

M5_dffs[2] = AMPP_FUNCTION(A1L5, M5_dffs[3], HB1_state[0], HB1_state[11]);


--M5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]
--operation mode is normal

M5_dffs[5] = AMPP_FUNCTION(A1L5, M5_dffs[6], HB1_state[0], HB1_state[11]);


--M5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]
--operation mode is normal

M5_dffs[4] = AMPP_FUNCTION(A1L5, M5_dffs[5], HB1_state[0], HB1_state[11]);


--C1L7 is sld_hub:sld_hub_inst|Equal~183
--operation mode is normal

C1L7 = AMPP_FUNCTION(M5_dffs[3], M5_dffs[2], M5_dffs[5], M5_dffs[4]);


--M5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]
--operation mode is normal

M5_dffs[0] = AMPP_FUNCTION(A1L5, M5_dffs[1], HB1_state[0], HB1_state[11]);


--JB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1]
--operation mode is normal

JB1_dffe1a[1] = AMPP_FUNCTION(A1L5, FB3_Q[1], C1L31, FB3_Q[2], FB3_Q[3], C1_CLRN_SIGNAL, C1L5);


--HB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
--operation mode is normal

HB1_state[8] = AMPP_FUNCTION(A1L5, HB1_state[5], HB1_state[7], VCC, !A1L7);


--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28
--operation mode is normal

C1L1 = AMPP_FUNCTION(HB1_state[8], C1_OK_TO_UPDATE_IR_Q, JB1_dffe1a[2], JB1_dffe1a[1]);


--A1L125 is Q1[0]~504
--operation mode is normal

A1L125 = DS1 & (Q1[6] $ DS0 # !Q1[7]) # !DS1 & (Q1[7] # Q1[6] $ DS0);


--FB5_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
--operation mode is normal

FB5_Q[3] = AMPP_FUNCTION(A1L5, FB7_Q[3], FB3_Q[3], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--MB1_ram_rom_data_shift_cntr_reg[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[1] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[1], !FB5_Q[3], MB1L4, MB1L45);

--MB1L47 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[1]~51
--operation mode is arithmetic

MB1L47 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[1], MB1L45);


--FB5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
--operation mode is normal

FB5_Q[1] = AMPP_FUNCTION(A1L5, FB7_Q[1], FB3_Q[1], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--MB1_ram_rom_data_shift_cntr_reg[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[0] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[0], MB1L14, !FB5_Q[3], MB1L4);

--MB1L45 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[0]~55
--operation mode is arithmetic

MB1L45 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[0], MB1L14);


--MB1_ram_rom_data_shift_cntr_reg[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]
--operation mode is arithmetic

MB1_ram_rom_data_shift_cntr_reg[2] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[2], !FB5_Q[3], MB1L4, MB1L47);

--MB1L49 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[2]~59
--operation mode is arithmetic

MB1L49 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[2], MB1L47);


--MB1_ram_rom_data_shift_cntr_reg[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_shift_cntr_reg[3]
--operation mode is normal

MB1_ram_rom_data_shift_cntr_reg[3] = AMPP_FUNCTION(A1L5, MB1_ram_rom_data_shift_cntr_reg[3], !FB5_Q[3], MB1L4, MB1L49);


--MB1L3 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|Equal~44
--operation mode is normal

MB1L3 = AMPP_FUNCTION(MB1_ram_rom_data_shift_cntr_reg[0], MB1_ram_rom_data_shift_cntr_reg[2], MB1_ram_rom_data_shift_cntr_reg[3]);


--MB1L13 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|process1~1
--operation mode is normal

MB1L13 = AMPP_FUNCTION(FB5_Q[3], MB1_ram_rom_data_shift_cntr_reg[1], FB5_Q[1], MB1L3);


--FB5L4 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209
--operation mode is normal

FB5L4 = AMPP_FUNCTION(FB5_Q[2], FB5_Q[1]);


--MB1L42 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]~885
--operation mode is normal

MB1L42 = AMPP_FUNCTION(FB5L4, HB1_state[4], MB1L53, MB1L13);


--MB1L52 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~0
--operation mode is normal

MB1L52 = AMPP_FUNCTION(FB5_Q[1], MB1L3, MB1_ram_rom_data_shift_cntr_reg[1]);


--MB1_ram_rom_incr_addr is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr
--operation mode is normal

MB1_ram_rom_incr_addr = AMPP_FUNCTION(MB1L52, HB1_state[8], FB5_Q[2], MB1L53);


--FB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]
--operation mode is normal

FB5_Q[0] = AMPP_FUNCTION(A1L5, FB7_Q[0], FB3_Q[0], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--MB1L12 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|process0~12
--operation mode is normal

MB1L12 = AMPP_FUNCTION(HB1_state[4], MB1L53, FB5_Q[3]);


--next_command.func_set is next_command.func_set
--operation mode is normal

next_command.func_set_lut_out = state.reset3 # next_command.func_set & (state.toggle_e # state.hold);
next_command.func_set = DFFEAS(next_command.func_set_lut_out, CLK_400HZ, !RES, , , , , , );


--next_command.reset2 is next_command.reset2
--operation mode is normal

next_command.reset2_lut_out = state.reset1 & (next_command.reset2 # !state.toggle_e & !state.hold);
next_command.reset2 = DFFEAS(next_command.reset2_lut_out, CLK_400HZ, !RES, , , , , , );


--next_command.reset3 is next_command.reset3
--operation mode is normal

next_command.reset3_lut_out = state.reset2 # next_command.reset3 & (state.toggle_e # state.hold);
next_command.reset3 = DFFEAS(next_command.reset3_lut_out, CLK_400HZ, !RES, , , , , , );


--next_command.display_on is next_command.display_on
--operation mode is normal

next_command.display_on_lut_out = state.display_clear # next_command.display_on & (state.toggle_e # state.hold);
next_command.display_on = DFFEAS(next_command.display_on_lut_out, CLK_400HZ, !RES, , , , , , );


--next_command.display_off is next_command.display_off
--operation mode is normal

next_command.display_off_lut_out = state.func_set # next_command.display_off & (state.toggle_e # state.hold);
next_command.display_off = DFFEAS(next_command.display_off_lut_out, CLK_400HZ, !RES, , , , , , );


--next_command.display_set is next_command.display_set
--operation mode is normal

next_command.display_set_lut_out = state.mode_set # state.return_home # next_command.display_set & !A1L140;
next_command.display_set = DFFEAS(next_command.display_set_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L140 is Select~2562