box.map.eqn

正弦波 发生器,VHDL的应用和处理,可以产生任意波形

LB1_q_b[6]_PORT_A_data_in = VCC;
LB1_q_b[6]_PORT_A_data_in_reg = DFFE(LB1_q_b[6]_PORT_A_data_in, LB1_q_b[6]_clock_0, , , );
LB1_q_b[6]_PORT_B_data_in = MB1_ram_rom_data_reg[6];
LB1_q_b[6]_PORT_B_data_in_reg = DFFE(LB1_q_b[6]_PORT_B_data_in, LB1_q_b[6]_clock_1, , , );
LB1_q_b[6]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[6]_PORT_A_address_reg = DFFE(LB1_q_b[6]_PORT_A_address, LB1_q_b[6]_clock_0, , , );
LB1_q_b[6]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[6]_PORT_B_address_reg = DFFE(LB1_q_b[6]_PORT_B_address, LB1_q_b[6]_clock_1, , , );
LB1_q_b[6]_PORT_A_write_enable = GND;
LB1_q_b[6]_PORT_A_write_enable_reg = DFFE(LB1_q_b[6]_PORT_A_write_enable, LB1_q_b[6]_clock_0, , , );
LB1_q_b[6]_PORT_B_write_enable = MB1L2;
LB1_q_b[6]_PORT_B_write_enable_reg = DFFE(LB1_q_b[6]_PORT_B_write_enable, LB1_q_b[6]_clock_1, , , );
LB1_q_b[6]_clock_0 = NB1__clk0;
LB1_q_b[6]_clock_1 = A1L5;
LB1_q_b[6]_PORT_B_data_out = MEMORY(LB1_q_b[6]_PORT_A_data_in_reg, LB1_q_b[6]_PORT_B_data_in_reg, LB1_q_b[6]_PORT_A_address_reg, LB1_q_b[6]_PORT_B_address_reg, LB1_q_b[6]_PORT_A_write_enable_reg, LB1_q_b[6]_PORT_B_write_enable_reg, , , LB1_q_b[6]_clock_0, LB1_q_b[6]_clock_1, , , , );
LB1_q_b[6] = LB1_q_b[6]_PORT_B_data_out[0];


--LB1_q_a[7] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_a[7]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 1, Port B Depth: 256, Port B Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
LB1_q_a[7]_PORT_A_data_in = VCC;
LB1_q_a[7]_PORT_A_data_in_reg = DFFE(LB1_q_a[7]_PORT_A_data_in, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7]_PORT_B_data_in = MB1_ram_rom_data_reg[7];
LB1_q_a[7]_PORT_B_data_in_reg = DFFE(LB1_q_a[7]_PORT_B_data_in, LB1_q_a[7]_clock_1, , , );
LB1_q_a[7]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_a[7]_PORT_A_address_reg = DFFE(LB1_q_a[7]_PORT_A_address, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_a[7]_PORT_B_address_reg = DFFE(LB1_q_a[7]_PORT_B_address, LB1_q_a[7]_clock_1, , , );
LB1_q_a[7]_PORT_A_write_enable = GND;
LB1_q_a[7]_PORT_A_write_enable_reg = DFFE(LB1_q_a[7]_PORT_A_write_enable, LB1_q_a[7]_clock_0, , , );
LB1_q_a[7]_PORT_B_write_enable = MB1L2;
LB1_q_a[7]_PORT_B_write_enable_reg = DFFE(LB1_q_a[7]_PORT_B_write_enable, LB1_q_a[7]_clock_1, , , );
LB1_q_a[7]_clock_0 = NB1__clk0;
LB1_q_a[7]_clock_1 = A1L5;
LB1_q_a[7]_PORT_A_data_out = MEMORY(LB1_q_a[7]_PORT_A_data_in_reg, LB1_q_a[7]_PORT_B_data_in_reg, LB1_q_a[7]_PORT_A_address_reg, LB1_q_a[7]_PORT_B_address_reg, LB1_q_a[7]_PORT_A_write_enable_reg, LB1_q_a[7]_PORT_B_write_enable_reg, , , LB1_q_a[7]_clock_0, LB1_q_a[7]_clock_1, , , , );
LB1_q_a[7] = LB1_q_a[7]_PORT_A_data_out[0];

--LB1_q_b[7] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|altsyncram_sfa2:altsyncram1|q_b[7]
LB1_q_b[7]_PORT_A_data_in = VCC;
LB1_q_b[7]_PORT_A_data_in_reg = DFFE(LB1_q_b[7]_PORT_A_data_in, LB1_q_b[7]_clock_0, , , );
LB1_q_b[7]_PORT_B_data_in = MB1_ram_rom_data_reg[7];
LB1_q_b[7]_PORT_B_data_in_reg = DFFE(LB1_q_b[7]_PORT_B_data_in, LB1_q_b[7]_clock_1, , , );
LB1_q_b[7]_PORT_A_address = BUS(Q1[0], Q1[1], Q1[2], Q1[3], Q1[4], Q1[5], Q1[6], Q1[7]);
LB1_q_b[7]_PORT_A_address_reg = DFFE(LB1_q_b[7]_PORT_A_address, LB1_q_b[7]_clock_0, , , );
LB1_q_b[7]_PORT_B_address = BUS(MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], MB1_ram_rom_addr_reg[5], MB1_ram_rom_addr_reg[6], MB1_ram_rom_addr_reg[7]);
LB1_q_b[7]_PORT_B_address_reg = DFFE(LB1_q_b[7]_PORT_B_address, LB1_q_b[7]_clock_1, , , );
LB1_q_b[7]_PORT_A_write_enable = GND;
LB1_q_b[7]_PORT_A_write_enable_reg = DFFE(LB1_q_b[7]_PORT_A_write_enable, LB1_q_b[7]_clock_0, , , );
LB1_q_b[7]_PORT_B_write_enable = MB1L2;
LB1_q_b[7]_PORT_B_write_enable_reg = DFFE(LB1_q_b[7]_PORT_B_write_enable, LB1_q_b[7]_clock_1, , , );
LB1_q_b[7]_clock_0 = NB1__clk0;
LB1_q_b[7]_clock_1 = A1L5;
LB1_q_b[7]_PORT_B_data_out = MEMORY(LB1_q_b[7]_PORT_A_data_in_reg, LB1_q_b[7]_PORT_B_data_in_reg, LB1_q_b[7]_PORT_A_address_reg, LB1_q_b[7]_PORT_B_address_reg, LB1_q_b[7]_PORT_A_write_enable_reg, LB1_q_b[7]_PORT_B_write_enable_reg, , , LB1_q_b[7]_clock_0, LB1_q_b[7]_clock_1, , , , );
LB1_q_b[7] = LB1_q_b[7]_PORT_B_data_out[0];


--A1L90Q is LCD_RS~reg0
--operation mode is normal

A1L90Q_lut_out = A1L159 & (A1L161 # A1L90Q & !A1L160) # !A1L159 & (A1L90Q & !A1L160);
A1L90Q = DFFEAS(A1L90Q_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L88Q is LCD_E~reg0
--operation mode is normal

A1L88Q_lut_out = state.display_set & (A1L88Q) # !state.display_set & (state.hold & (A1L88Q) # !state.hold & state.toggle_e);
A1L88Q = DFFEAS(A1L88Q_lut_out, CLK_400HZ, !RES, , , , , , );


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);


--HB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

HB1_state[5] = AMPP_FUNCTION(A1L5, A1L7, HB1_state[4], HB1_state[3], VCC);


--FB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

FB5_Q[2] = AMPP_FUNCTION(A1L5, FB7_Q[2], FB3_Q[2], FB2_Q[0], C1_CLRN_SIGNAL, C1L25);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, C1L31, C1_jtag_debug_mode, C1L32, HB1_state[15], HB1_state[0]);


--FB8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

FB8_Q[0] = AMPP_FUNCTION(A1L5, FB3_Q[8], altera_internal_jtag, C1_CLRN_SIGNAL, C1L23);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, M5_dffs[1], C1L6, C1L7, M5_dffs[0], HB1_state[0], HB1_state[12]);


--FB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

FB2_Q[0] = AMPP_FUNCTION(A1L5, JB1_dffe1a[1], FB2_Q[0], FB9_Q[0], C1L1, C1_CLRN_SIGNAL);


--MB1L53 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~21
--operation mode is normal

MB1L53 = AMPP_FUNCTION(C1_jtag_debug_mode, FB8_Q[0], C1_jtag_debug_mode_usr1, FB2_Q[0]);


--MB1L2 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11
--operation mode is normal

MB1L2 = AMPP_FUNCTION(HB1_state[5], FB5_Q[2], MB1L53);


--NB1__clk0 is PLLU:u2|altpll:altpll_component|_clk0
NB1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(RES), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(CLK), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--Q1[0] is Q1[0]
--operation mode is arithmetic

Q1[0]_lut_out = !Q1[0];
Q1[0] = DFFEAS(Q1[0]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L124 is Q1[0]~473
--operation mode is arithmetic

A1L124 = CARRY(Q1[0]);


--Q1[1] is Q1[1]
--operation mode is arithmetic

Q1[1]_carry_eqn = A1L124;
Q1[1]_lut_out = Q1[1] $ (Q1[1]_carry_eqn);
Q1[1] = DFFEAS(Q1[1]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L127 is Q1[1]~477
--operation mode is arithmetic

A1L127 = CARRY(!A1L124 # !Q1[1]);


--Q1[2] is Q1[2]
--operation mode is arithmetic

Q1[2]_carry_eqn = A1L127;
Q1[2]_lut_out = Q1[2] $ (!Q1[2]_carry_eqn);
Q1[2] = DFFEAS(Q1[2]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L129 is Q1[2]~481
--operation mode is arithmetic

A1L129 = CARRY(Q1[2] & (!A1L127));


--Q1[3] is Q1[3]
--operation mode is arithmetic

Q1[3]_carry_eqn = A1L129;
Q1[3]_lut_out = Q1[3] $ (Q1[3]_carry_eqn);
Q1[3] = DFFEAS(Q1[3]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L131 is Q1[3]~485
--operation mode is arithmetic

A1L131 = CARRY(!A1L129 # !Q1[3]);


--Q1[4] is Q1[4]
--operation mode is arithmetic

Q1[4]_carry_eqn = A1L131;
Q1[4]_lut_out = Q1[4] $ (!Q1[4]_carry_eqn);
Q1[4] = DFFEAS(Q1[4]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L133 is Q1[4]~489
--operation mode is arithmetic

A1L133 = CARRY(Q1[4] & (!A1L131));


--Q1[5] is Q1[5]
--operation mode is arithmetic

Q1[5]_carry_eqn = A1L133;
Q1[5]_lut_out = Q1[5] $ (Q1[5]_carry_eqn);
Q1[5] = DFFEAS(Q1[5]_lut_out, NB1__clk0, VCC, , , ~GND, , , A1L125);

--A1L135 is Q1[5]~493
--operation mode is arithmetic

A1L135 = CARRY(!A1L133 # !Q1[5]);


--Q1[6] is Q1[6]
--operation mode is arithmetic

Q1[6]_carry_eqn = A1L135;
Q1[6]_lut_out = Q1[6] $ (!Q1[6]_carry_eqn);
Q1[6] = DFFEAS(Q1[6]_lut_out, NB1__clk0, VCC, , , DS0, , , A1L125);

--A1L137 is Q1[6]~497
--operation mode is arithmetic

A1L137 = CARRY(Q1[6] & (!A1L135));


--Q1[7] is Q1[7]
--operation mode is normal

Q1[7]_carry_eqn = A1L137;
Q1[7]_lut_out = Q1[7] $ (Q1[7]_carry_eqn);
Q1[7] = DFFEAS(Q1[7]_lut_out, NB1__clk0, VCC, , , DS1, , , A1L125);


--MB1_ram_rom_data_reg[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

MB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, LB1_q_b[0], MB1_ram_rom_data_reg[1], MB1L13, VCC, MB1L42);


--MB1_ram_rom_addr_reg[0] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[0] = AMPP_FUNCTION(A1L5, MB1_ram_rom_incr_addr, MB1_ram_rom_addr_reg[0], MB1_ram_rom_addr_reg[1], !FB5_Q[0], MB1L12);

--MB1L19 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~121
--operation mode is arithmetic

MB1L19 = AMPP_FUNCTION(MB1_ram_rom_incr_addr, MB1_ram_rom_addr_reg[0]);


--MB1_ram_rom_addr_reg[1] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[1] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[1], MB1_ram_rom_addr_reg[2], !FB5_Q[0], MB1L12, MB1L19);

--MB1L21 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~125
--operation mode is arithmetic

MB1L21 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[1], MB1L19);


--MB1_ram_rom_addr_reg[2] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[2] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[2], MB1_ram_rom_addr_reg[3], !FB5_Q[0], MB1L12, MB1L21);

--MB1L23 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~129
--operation mode is arithmetic

MB1L23 = AMPP_FUNCTION(MB1_ram_rom_addr_reg[2], MB1L21);


--MB1_ram_rom_addr_reg[3] is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]
--operation mode is arithmetic

MB1_ram_rom_addr_reg[3] = AMPP_FUNCTION(A1L5, MB1_ram_rom_addr_reg[3], MB1_ram_rom_addr_reg[4], !FB5_Q[0], MB1L12, MB1L23);

--MB1L25 is allwave:u1|altsyncram:altsyncram_component|altsyncram_dpu:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~133
--operation mode is arithmetic