mux21w16.vhd

来自「可综合FFT的VHDL实现 已经过测试」· VHDL 代码 · 共 40 行

-- output of CoreGen module generator
-- $Header: mux2VHT.vhd,v 1.2 1998/06/15 17:57:53 tonyw Exp $
-- ************************************************************************
--  Copyright 1996-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--    Two input mux
--                                        

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

LIBRARY xul;
USE xul.ul_utils.ALL;

ENTITY mux21w16 IS
  PORT( d0 : IN  std_logic_vector( 16 - 1 DOWNTO 0 );
        d1 : IN  std_logic_vector( 16 - 1 DOWNTO 0 );
        s0 : IN  std_logic;
        o : OUT std_logic_vector( 16 - 1 DOWNTO 0 ) );
END mux21w16;


ARCHITECTURE behv OF mux21w16 IS
CONSTANT w: integer := 16;
BEGIN
 process (d0, d1, s0)
 begin
  case rat(s0) is
    WHEN '0' => o <= d0;
    WHEN '1' => o <= d1;
    WHEN OTHERS => o <= setallX(w);
  end case;
 end process;
end behv;