fftwrap.vhd

可综合FFT的VHDL实现 已经过测试

library ieee;
use ieee.std_logic_1164.all;


entity fftwrap is
  port (
	RS   		: in    std_logic;
	DR     	: in std_logic_vector(15 downto 0);
	DI     	: in std_logic_vector(15 downto 0);
	START   	: in    std_logic;
	CE   		: in    std_logic;
	CLK   	: in    std_logic;
	FRAME 	: out    std_logic;
	XK_R  	: out    std_logic_vector(15 downto 0);
	XK_I  	: out    std_logic_vector(15 downto 0)
       );

end fftwrap;


architecture WRAPPER of fftwrap is

   component xfft16
      port (
        RS   : in    std_logic;
        DR15     : in std_logic;
        DR14     : in std_logic;
        DR13     : in std_logic;
        DR12     : in std_logic;
        DR11     : in std_logic;
        DR10     : in std_logic;
        DR9     : in std_logic;
        DR8     : in std_logic;
        DR7     : in std_logic;
        DR6     : in std_logic;
        DR5     : in std_logic;
        DR4     : in std_logic;
        DR3     : in std_logic;
        DR2     : in std_logic;
        DR1     : in std_logic;
        DR0     : in std_logic;
        DI15     : in std_logic;
        DI14     : in std_logic;
        DI13     : in std_logic;
        DI12     : in std_logic;
        DI11     : in std_logic;
        DI10     : in std_logic;
        DI9     : in std_logic;
        DI8     : in std_logic;
        DI7     : in std_logic;
        DI6     : in std_logic;
        DI5     : in std_logic;
        DI4     : in std_logic;
        DI3     : in std_logic;
        DI2     : in std_logic;
        DI1     : in std_logic;
        DI0     : in std_logic;
        START     : in std_logic;
        CE        : in std_logic;
        CLK       : in std_logic;
        FRAME    : out std_logic;
        XK_R15  : out std_logic;
        XK_R14  : out std_logic;
        XK_R13  : out std_logic;
        XK_R12  : out std_logic;
        XK_R11  : out std_logic;
        XK_R10  : out std_logic;
        XK_R9  : out std_logic;
        XK_R8  : out std_logic;
        XK_R7  : out std_logic;
        XK_R6  : out std_logic;
        XK_R5 : out std_logic;
        XK_R4  : out std_logic;
        XK_R3  : out std_logic;
        XK_R2  : out std_logic;
        XK_R1  : out std_logic;
        XK_R0  : out std_logic;
        XK_I15  : out std_logic;
        XK_I14  : out std_logic;
        XK_I13  : out std_logic;
        XK_I12  : out std_logic;
        XK_I11  : out std_logic;
        XK_I10  : out std_logic;
        XK_I9  : out std_logic;
        XK_I8  : out std_logic;
        XK_I7  : out std_logic;
        XK_I6  : out std_logic;
        XK_I5  : out std_logic;
        XK_I4  : out std_logic;
        XK_I3  : out std_logic;
        XK_I2  : out std_logic;
        XK_I1  : out std_logic;
        XK_I0  : out std_logic      
	) ;
         end component;

begin

  FFT16: xfft16
    port map (
        RS   	=> RS ,
        DR15    => DR(15) ,
        DR14    => DR(14) ,
        DR13    => DR(13) ,
        DR12    => DR(12) ,
        DR11    => DR(11) ,
        DR10    => DR(10) ,
        DR9     => DR(9) ,
        DR8     => DR(8) ,
        DR7     => DR(7) ,
        DR6     => DR(6) ,
        DR5     => DR(5) ,
        DR4     => DR(4) ,
        DR3     => DR(3) ,
        DR2     => DR(2) ,
        DR1     => DR(1) ,
        DR0     => DR(0) ,
        DI15    => DI(15) ,
        DI14    => DI(14) ,
        DI13    => DI(13) ,
        DI12    => DI(12) ,
        DI11    => DI(11) ,
        DI10    => DI(10) ,
        DI9     => DI(9) ,
        DI8     => DI(8) ,
        DI7     => DI(7) ,
        DI6     => DI(6) ,
        DI5     => DI(5) ,
        DI4     => DI(4) ,
        DI3     => DI(3) ,
        DI2     => DI(2) ,
        DI1     => DI(1) ,
        DI0     => DI(0) ,
        START   => START ,
        CE      => CE ,
        CLK     => CLK ,
        FRAME    => FRAME ,
        XK_R15   => XK_R(15) ,
        XK_R14   => XK_R(14) ,
        XK_R13   => XK_R(13) ,
        XK_R12   => XK_R(12) ,
        XK_R11   => XK_R(11) ,
        XK_R10   => XK_R(10) ,
        XK_R9    => XK_R(9) ,
        XK_R8    => XK_R(8) ,
        XK_R7    => XK_R(7) ,
        XK_R6    => XK_R(6) ,
        XK_R5    => XK_R(5) ,
        XK_R4    => XK_R(4) ,
        XK_R3    => XK_R(3) ,
        XK_R2    => XK_R(2) ,
        XK_R1    => XK_R(1) ,
        XK_R0    => XK_R(0) ,
        XK_I15   => XK_I(15) ,
        XK_I14   => XK_I(14) ,
        XK_I13   => XK_I(13) ,
        XK_I12   => XK_I(12) ,
        XK_I11   => XK_I(11) ,
        XK_I10   => XK_I(10) ,
        XK_I9    => XK_I(9) ,
        XK_I8    => XK_I(8) ,
        XK_I7    => XK_I(7) ,
        XK_I6    => XK_I(6) ,
        XK_I5    => XK_I(5) ,
        XK_I4    => XK_I(4) ,
        XK_I3    => XK_I(3) ,
        XK_I2    => XK_I(2) ,
        XK_I1    => XK_I(1) ,
        XK_I0    => XK_I(0) 
     );

end WRAPPER;