simulation.tdf

基于fpga的屏幕测试程序

include "fran_pg.inc";
include "lpm_counter.inc";
include "lpm_ram_dp.inc";
SUBDESIGN simulation
(   
	clk			    	: INPUT;
	HAC[10..0]			: INPUT;
	VAC[10..0]			: INPUT;
	act_hcounter[10..0] : INPUT;
	act_vcounter[10..0]	: INPUT;
    
	wren				: INPUT;
	wraddr[7..0]   		: INPUT;
	
	red_in[9..0]		: INPUT;
	green_in[9..0]		: INPUT;
	blue_in[9..0]		: INPUT;
	
	out_en				: OUTPUT;	
	red_out[9..0]		: OUTPUT;
	green_out[9..0]		: OUTPUT;
	blue_out[9..0]		: OUTPUT;	
)

VARIABLE
	smlt_r_ram,
	smlt_g_ram,
	smlt_b_ram 	: lpm_ram_dp WITH 
						  (
						   LPM_WIDTH = 10,
						   LPM_WIDTHAD = 8
						  );						
							   
 	out_enable				: NODE;
	rdaddr[7..0]			: NODE;
	rdaddr_11b[10..0]		: NODE;
	red_node_out[9..0]		: NODE;
	green_node_out[9..0]	: NODE;
	blue_node_out[9..0]		: NODE;
	
BEGIN
smlt_r_ram.wrclock = clk;
smlt_g_ram.wrclock = clk;
smlt_b_ram.wrclock = clk;
smlt_r_ram.wrclken = VCC;
smlt_g_ram.wrclken = VCC;
smlt_b_ram.wrclken = VCC;
smlt_r_ram.rdclock = clk;
smlt_g_ram.rdclock = clk;
smlt_b_ram.rdclock = clk;
smlt_r_ram.rdclken = VCC;
smlt_g_ram.rdclken = VCC;
smlt_b_ram.rdclken = VCC;

smlt_r_ram.wren			= wren;
smlt_g_ram.wren 		= wren;
smlt_b_ram.wren 		= wren;
smlt_r_ram.wraddress[] 	= wraddr[7..0];
smlt_g_ram.wraddress[] 	= wraddr[7..0];
smlt_b_ram.wraddress[] 	= wraddr[7..0];
smlt_r_ram.data[] 		= red_in[9..0];
smlt_g_ram.data[] 		= green_in[9..0];
smlt_b_ram.data[] 		= blue_in[9..0];

red_node_out[9..0]   = smlt_r_ram.q[9..0];
green_node_out[9..0] = smlt_g_ram.q[9..0];
blue_node_out[9..0]  = smlt_b_ram.q[9..0];
red_out[9..0]   	 = red_node_out[9..0];
green_out[9..0] 	 = green_node_out[9..0];
blue_out[9..0]  	 = blue_node_out[9..0];
		
IF (act_vcounter[] >= (0,VAC[10..1])-50) AND (act_vcounter[] <= (0,VAC[10..1])+50) THEN 
	IF (act_hcounter[] >= (0,HAC[10..1])-100) AND (act_hcounter[] < (0,HAC[10..1])+100)
		THEN  out_enable = VCC;
			  rdaddr_11b[10..0] = act_hcounter[]-(0,VAC[10..1])-100;
	END IF;
ELSE out_enable = GND;
	 rdaddr_11b[10..0] = 0;
END IF;
rdaddr[7..0] = rdaddr_11b[7..0];
smlt_r_ram.rdaddress[] = rdaddr[7..0];
smlt_g_ram.rdaddress[] = rdaddr[7..0];
smlt_b_ram.rdaddress[] = rdaddr[7..0];

out_en = out_enable;

END;