cyclic.drc.rpt

基于fpga的屏幕测试程序

; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|addressed~245                      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|sum[2]      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|sdap                               ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|read~53                            ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|byteCounter[0]~293                 ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|shiftOutReg                        ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|shiftInReg[7]                      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cregout:expander_data|reg[0]                               ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|shiftInReg[6]                      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|waitCounter[2]                     ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|waitCounter[0]                     ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|waitCounter[1]                     ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|waitff                             ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1]      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|sum[1]      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[0]      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|shiftReg[4] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|sum[0]      ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[4] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|shiftReg[3] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|shiftReg[2] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[3] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[2] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|shiftReg[1] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[1] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|shiftReg[0] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] ;
; Design should not contain ripple clock structures - Structure1 ; expander:i2c_expander|i2cregout:expander_data|reg[7]                               ;
; Clock signal source should drive only input clock ports        ; fran_pg:pattern_generator|vsync_art                                                ;
; Clock signal source should drive only input clock ports        ; expander:i2c_expander|klok_div_8[2]                                                ;
; Clock signal source should drive only input clock ports        ; expander:i2c_expander|klok_div_8[1]                                                ;
; Clock signal source should drive only input clock ports        ; expander:i2c_expander|klok_div_8[0]                                                ;
; Clock signal source should drive only input clock ports        ; clk1_in                                                                            ;
; Clock signal source should drive only input clock ports        ; dclk                                                                               ;
+----------------------------------------------------------------+------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only Violations                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Rule name                                                                                                             ; Name                                                                                                                                                                                                       ;
+-----------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Red_art[0]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; r_e_o_pg[1]                                                                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Red_art[1]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|fullregbuf[11]                                                                                                                                                                   ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|importN7bits:fullreg|Xoutbuf01[4]                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|certaingrayscales:theCertainGrayscale2|Red_dff[2]                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Red_on                                                                                                                                                                           ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|fullregbuf[7]                                                                                                                                                                    ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; g_e_o_pg[0]                                                                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Gre_art[0]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; g_e_o_pg[1]                                                                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Gre_art[1]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Gre_on                                                                                                                                                                           ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|fullregbuf[8]                                                                                                                                                                    ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; b_e_o_pg[0]                                                                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Blu_art[0]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; b_e_o_pg[1]                                                                                                                                                                                                ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Blu_art[1]                                                                                                                                                                       ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|Blu_on                                                                                                                                                                           ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|fullregbuf[9]                                                                                                                                                                    ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; de_out_pg                                                                                                                                                                                                  ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|nblank_art_delay[4]                                                                                                                                                              ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; hsync_out_pg                                                                                                                                                                                               ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|hsync_art                                                                                                                                                                        ;
; Register output directly drives input of another register when both registers are triggered at same time - Structure1 ; fran_pg:pattern_generator|fullregbuf[13]                                                                                                                                                                   ;