cyclic.drc.rpt

基于fpga的屏幕测试程序

; External reset should be synchronized using two cascaded registers                                                                                                                                                                                                             ; On           ;
; External reset should be correctly synchronized                                                                                                                                                                                                                                ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized                                                                                                                                                        ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized                                                                                                                                              ; On           ;
; Nodes with more than specified number of fan-outs                                                                                                                                                                                                                              ; Off          ;
; Top nodes with highest fan-out                                                                                                                                                                                                                                                 ; Off          ;
; Register output directly drives input of another register when both registers are triggered at same time                                                                                                                                                                       ; On           ;
; Registers in direct data transfer between clock domains are triggered by clock edges at the same time                                                                                                                                                                          ; On           ;
; Design should not contain combinational loops                                                                                                                                                                                                                                  ; On           ;
; Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                                ; On           ;
; Design should not contain delay chains                                                                                                                                                                                                                                         ; On           ;
; Design should not contain ripple clock structures                                                                                                                                                                                                                              ; On           ;
; Pulses should not be implemented asynchronously                                                                                                                                                                                                                                ; On           ;
; Multiple pulses should not be generated in design                                                                                                                                                                                                                              ; On           ;
; Design should not contain SR latches                                                                                                                                                                                                                                           ; On           ;
; Design should not contain latches                                                                                                                                                                                                                                              ; On           ;
; Combinational logic should not directly drive write enable signal of asynchronous RAM                                                                                                                                                                                          ; On           ;
; Design should not contain asynchronous memory                                                                                                                                                                                                                                  ; On           ;
; Output enable and input of same tri-state node should not be driven by same signal source                                                                                                                                                                                      ; On           ;
; Synchronous port and reset port of same register should not be driven by same signal source                                                                                                                                                                                    ; On           ;
; Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                             ; On           ;
; Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain                                                                                                                          ; On           ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                   ; On           ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On           ;
; PLL drives multiple clock network types (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                                  ; On           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Critical Violations                                                                                                                            ;
+---------------------------------------------------------------------+--------------------------------------------------------------------------+
; Rule name                                                           ; Name                                                                     ;
+---------------------------------------------------------------------+--------------------------------------------------------------------------+
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[0]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[1]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[2]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[3]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[4]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[5]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[6]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[7]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|counti[8]             ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|fullregbuf[74]~_DUP_COMB                       ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~209               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~204               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|LessThan~190          ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~219               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|LessThan~215          ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|LessThan~198          ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|LessThan~198COUT1_383 ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~199               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~216               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~206               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~206COUT1_387      ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~201               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~211               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~201COUT1_389      ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~211COUT1_385      ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~214               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~226               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~226COUT1_383      ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~224               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~231               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~231COUT1_381      ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~229               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~236               ;
; Design should not contain combinational loops - Combinational loop1 ; fran_pg:pattern_generator|pattern_dl:thepattern_dl|add~236COUT1_379      ;