varloadblocks.tdf

基于fpga的屏幕测试程序

-- varloadblocks.tdf
-- to define the valid area 
-- based on EF and AVD's original work
-- Zhang Yuning
-- 2005-4-11

-- revised by Chai Lin
-- 8-27-2006

include "fran_pg.inc";
include "lpm_compare";

SUBDESIGN varloadblocks
(	
	clk			    	: INPUT;
	blocksize[6..0]	    : INPUT;
	h_sta[11..0]	    : INPUT;
	h_end[11..0]	    : INPUT;
	v_sta[11..0]	    : INPUT;
	v_end[11..0]	    : INPUT;
	act_vcounter[10..0]	: INPUT;
	act_hcounter[10..0] : INPUT;
	
	henable             : OUTPUT;
	venable             : OUTPUT;
)

VARIABLE
	
	
	vload1, vload2,
    hload1, hload2
     			: lpm_compare WITH (
				                    LPM_WIDTH = 11,
									ONE_INPUT_IS_CONSTANT = "YES",
									LPM_REPRESENTATION = "UNSIGNED",
									LPM_PIPELINE = 2
									);
	hloadblock 		: 	SRFF;
	vloadblock 		: 	SRFF;
	--loadhsta[10..0]	:	NODE;
	--loadhend[10..0]	:	NODE;              
	--loadvsta[10..0]	:	NODE;
	--loadvend[10..0]	:	NODE;
	
BEGIN

    vload1.dataa[10..0] = act_vcounter[10..0];
    vload1.datab[10..0] = v_sta[10..0];
    vload1.clock = clk;

    vload2.dataa[10..0] = act_vcounter[10..0];
    vload2.datab[10..0] = v_end[10..0];
    vload2.clock = clk;

    hload1.dataa[10..0] = act_hcounter[10..0];
    hload1.datab[10..0] = h_sta[10..0];
    hload1.clock = clk;

    hload2.dataa[10..0] = act_hcounter[10..0];
    hload2.datab[10..0] = h_end[10..0];
    hload2.clock = clk;

    hloadblock.clk = clk;
    hloadblock.S   = hload1.aeb;
    hloadblock.R   = hload2.aeb;

    vloadblock.clk = clk;
    vloadblock.S   = vload1.aeb;
    vloadblock.R   = vload2.aeb;
    
    CASE blocksize[6..0] IS
    WHEN 0 =>
         henable = GND;
         venable = GND;
    WHEN 101 =>
         henable = GND;
         venable = GND;
    WHEN OTHERS =>
         henable = hloadblock.q;
         venable = vloadblock.q;        
    END CASE;   

END;