alt_u_div_3pd.tdf

基于fpga的屏幕测试程序

	remainder[8..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_ke8;
	add_sub_1 : add_sub_le8;
	add_sub_10 : add_sub_4g8;
	add_sub_11 : add_sub_4g8;
	add_sub_12 : add_sub_4g8;
	add_sub_13 : add_sub_4g8;
	add_sub_14 : add_sub_4g8;
	add_sub_15 : add_sub_4g8;
	add_sub_16 : add_sub_4g8;
	add_sub_17 : add_sub_4g8;
	add_sub_18 : add_sub_4g8;
	add_sub_2 : add_sub_me8;
	add_sub_3 : add_sub_ne8;
	add_sub_4 : add_sub_oe8;
	add_sub_5 : add_sub_pe8;
	add_sub_6 : add_sub_qe8;
	add_sub_7 : add_sub_re8;
	add_sub_8 : add_sub_se8;
	add_sub_9 : add_sub_4g8;
	DenominatorIn[199..0]	: WIRE;
	DenominatorIn_tmp[199..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[379..0]	: WIRE;
	NumeratorIn[379..0]	: WIRE;
	NumeratorIn_tmp[379..0]	: WIRE;
	prestg[189..0]	: WIRE;
	quotient_tmp[18..0]	: WIRE;
	sel[179..0]	: WIRE;
	selnose[379..0]	: WIRE;
	StageIn[199..0]	: WIRE;
	StageIn_tmp[199..0]	: WIRE;
	StageOut[189..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[18..18];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[10..10], NumeratorIn[36..36]);
	add_sub_1.datab[1..0] = DenominatorIn[11..10];
	add_sub_10.dataa[] = ( StageIn[108..100], NumeratorIn[198..198]);
	add_sub_10.datab[9..0] = DenominatorIn[109..100];
	add_sub_11.dataa[] = ( StageIn[118..110], NumeratorIn[216..216]);
	add_sub_11.datab[9..0] = DenominatorIn[119..110];
	add_sub_12.dataa[] = ( StageIn[128..120], NumeratorIn[234..234]);
	add_sub_12.datab[9..0] = DenominatorIn[129..120];