cyclic.map.qmsg

基于fpga的屏幕测试程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\"" {  } { { "altdpram.tdf" "ram_block" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 182 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0ih1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_0ih1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0ih1 " "Info: Found entity 1: altsyncram_0ih1" {  } { { "db/altsyncram_0ih1.tdf" "" { Text "D:/实验室/pg_070731/db/altsyncram_0ih1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0ih1 fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_0ih1:auto_generated " "Info: Elaborating entity \"altsyncram_0ih1\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_0ih1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mov_ram_g.vhd 2 1 " "Info: Using design file mov_ram_g.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mov_ram_g-SYN " "Info: Found design unit 1: mov_ram_g-SYN" {  } { { "mov_ram_g.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_g.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 mov_ram_g " "Info: Found entity 1: mov_ram_g" {  } { { "mov_ram_g.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_g.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mov_ram_g fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_g:u1_2 " "Info: Elaborating entity \"mov_ram_g\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_g:u1_2\"" {  } { { "moving_object.vhd" "u1_2" { Text "D:/实验室/pg_070731/moving_object.vhd" 192 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mov_ram_b.vhd 2 1 " "Info: Using design file mov_ram_b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mov_ram_b-SYN " "Info: Found design unit 1: mov_ram_b-SYN" {  } { { "mov_ram_b.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_b.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 mov_ram_b " "Info: Found entity 1: mov_ram_b" {  } { { "mov_ram_b.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_b.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mov_ram_b fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_b:u1_3 " "Info: Elaborating entity \"mov_ram_b\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_b:u1_3\"" {  } { { "moving_object.vhd" "u1_3" { Text "D:/实验室/pg_070731/moving_object.vhd" 205 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "sim_ram_r.vhd 2 1 " "Info: Using design file sim_ram_r.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sim_ram_r-SYN " "Info: Found design unit 1: sim_ram_r-SYN" {  } { { "sim_ram_r.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_r.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sim_ram_r " "Info: Found entity 1: sim_ram_r" {  } { { "sim_ram_r.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_r.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sim_ram_r fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1 " "Info: Elaborating entity \"sim_ram_r\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\"" {  } { { "moving_object.vhd" "u2_1" { Text "D:/实验室/pg_070731/moving_object.vhd" 219 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\"" {  } { { "sim_ram_r.vhd" "alt3pram_component" { Text "D:/实验室/pg_070731/sim_ram_r.vhd" 102 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdpram fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1 " "Info: Elaborating entity \"altdpram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\"" {  } { { "alt3pram.tdf" "altdpram_component1" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 184 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\"" {  } { { "altdpram.tdf" "ram_block" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 182 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lhh1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lhh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lhh1 " "Info: Found entity 1: altsyncram_lhh1" {  } { { "db/altsyncram_lhh1.tdf" "" { Text "D:/实验室/pg_070731/db/altsyncram_lhh1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lhh1 fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_lhh1:auto_generated " "Info: Elaborating entity \"altsyncram_lhh1\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_r:u2_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_lhh1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "sim_ram_g.vhd 2 1 " "Info: Using design file sim_ram_g.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sim_ram_g-SYN " "Info: Found design unit 1: sim_ram_g-SYN" {  } { { "sim_ram_g.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_g.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sim_ram_g " "Info: Found entity 1: sim_ram_g" {  } { { "sim_ram_g.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_g.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sim_ram_g fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_g:u2_2 " "Info: Elaborating entity \"sim_ram_g\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_g:u2_2\"" {  } { { "moving_object.vhd" "u2_2" { Text "D:/实验室/pg_070731/moving_object.vhd" 232 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "sim_ram_b.vhd 2 1 " "Info: Using design file sim_ram_b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sim_ram_b-SYN " "Info: Found design unit 1: sim_ram_b-SYN" {  } { { "sim_ram_b.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_b.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sim_ram_b " "Info: Found entity 1: sim_ram_b" {  } { { "sim_ram_b.vhd" "" { Text "D:/实验室/pg_070731/sim_ram_b.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sim_ram_b fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_b:u2_3 " "Info: Elaborating entity \"sim_ram_b\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|sim_ram_b:u2_3\"" {  } { { "moving_object.vhd" "u2_3" { Text "D:/实验室/pg_070731/moving_object.vhd" 245 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pattern_dl fran_pg:pattern_generator\|pattern_dl:thepattern_dl " "Info: Elaborating entity \"pattern_dl\" for hierarchy \"fran_pg:pattern_generator\|pattern_dl:thepattern_dl\"" {  } { { "fran_pg.tdf" "thepattern_dl" { Text "D:/实验室/pg_070731/fran_pg.tdf" 132 1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counti pattern_dl.vhd(138) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(138): signal \"counti\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data_length pattern_dl.vhd(138) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(138): signal \"data_length\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counti pattern_dl.vhd(139) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(139): signal \"counti\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "counti pattern_dl.vhd(144) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(144): signal \"counti\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 144 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "counti pattern_dl.vhd(135) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(135): signal or variable \"counti\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"counti\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 135 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "start pattern_dl.vhd(135) " "Warning: VHDL Process Statement warning at pattern_dl.vhd(135): signal or variable \"start\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"start\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "pattern_dl.vhd" "" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 135 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_red fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr " "Info: Elaborating entity \"data_red\" for hierarchy \"fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\"" {  } { { "pattern_dl.vhd" "dr" { Text "D:/实验室/pg_070731/pattern_dl.vhd" 99 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component\"" {  } { { "data_red.vhd" "alt3pram_component" { Text "D:/实验室/pg_070731/data_red.vhd" 101 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdpram fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component\|altdpram:altdpram_component1 " "Info: Elaborating entity \"altdpram\" for hierarchy \"fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\"" {  } { { "alt3pram.tdf" "altdpram_component1" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 184 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"fran_pg:pattern_generator\|pattern_dl:thepattern_dl\|data_red:dr\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\"" {  } { { "altdpram.tdf" "ram_block" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 182 4 0 } }  } 0}