cyclic.map.qmsg

基于fpga的屏幕测试程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "certaingrayscales.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file certaingrayscales.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 certaingrayscales " "Info: Found entity 1: certaingrayscales" {  } { { "certaingrayscales.tdf" "" { Text "D:/实验室/pg_070731/certaingrayscales.tdf" 5 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rgbramps.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rgbramps.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 rgbramps " "Info: Found entity 1: rgbramps" {  } { { "rgbramps.tdf" "" { Text "D:/实验室/pg_070731/rgbramps.tdf" 11 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "importN7bits.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file importN7bits.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 importN7bits " "Info: Found entity 1: importN7bits" {  } { { "importN7bits.tdf" "" { Text "D:/实验室/pg_070731/importN7bits.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hmovingbars.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file hmovingbars.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 hmovingbars " "Info: Found entity 1: hmovingbars" {  } { { "hmovingbars.tdf" "" { Text "D:/实验室/pg_070731/hmovingbars.tdf" 11 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vmovingbars.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file vmovingbars.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 vmovingbars " "Info: Found entity 1: vmovingbars" {  } { { "vmovingbars.tdf" "" { Text "D:/实验室/pg_070731/vmovingbars.tdf" 12 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hbars.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file hbars.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 hbars " "Info: Found entity 1: hbars" {  } { { "hbars.tdf" "" { Text "D:/实验室/pg_070731/hbars.tdf" 12 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vbars.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file vbars.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 vbars " "Info: Found entity 1: vbars" {  } { { "vbars.tdf" "" { Text "D:/实验室/pg_070731/vbars.tdf" 12 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cyclic " "Info: Elaborating entity \"cyclic\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cnt cyclic.vhd(66) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(66): object \"cnt\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 66 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cnt_rst cyclic.vhd(67) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(67): object \"cnt_rst\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 67 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "input_var cyclic.vhd(80) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(80): object \"input_var\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 80 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "output_buf_r_o_pg cyclic.vhd(105) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(105): object \"output_buf_r_o_pg\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 105 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "output_buf_g_o_pg cyclic.vhd(106) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(106): object \"output_buf_g_o_pg\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 106 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "output_buf_b_o_pg cyclic.vhd(107) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(107): object \"output_buf_b_o_pg\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 107 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "PWDN_buf_pg cyclic.vhd(113) " "Info: (10035) Verilog HDL or VHDL information at cyclic.vhd(113): object \"PWDN_buf_pg\" declared but not used" {  } { { "cyclic.vhd" "" { Text "D:/实验室/pg_070731/cyclic.vhd" 113 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "expander expander:i2c_expander " "Info: Elaborating entity \"expander\" for hierarchy \"expander:i2c_expander\"" {  } { { "cyclic.vhd" "i2c_expander" { Text "D:/实验室/pg_070731/cyclic.vhd" 224 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2cSlave expander:i2c_expander\|i2cSlave:I2Cslavecore_one " "Info: Elaborating entity \"i2cSlave\" for hierarchy \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\"" {  } { { "expander.tdf" "I2Cslavecore_one" { Text "D:/实验室/pg_070731/expander.tdf" 27 1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "medianFilter expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian " "Info: Elaborating entity \"medianFilter\" for hierarchy \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\"" {  } { { "i2cslave.tdf" "sdaMedian" { Text "D:/实验室/pg_070731/i2cslave.tdf" 156 4 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2cregout expander:i2c_expander\|i2cregout:expander_data " "Info: Elaborating entity \"i2cregout\" for hierarchy \"expander:i2c_expander\|i2cregout:expander_data\"" {  } { { "expander.tdf" "expander_data" { Text "D:/实验室/pg_070731/expander.tdf" 28 1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RGB10to10 RGB10to10:rgb10bitsconverter " "Info: Elaborating entity \"RGB10to10\" for hierarchy \"RGB10to10:rgb10bitsconverter\"" {  } { { "cyclic.vhd" "rgb10bitsconverter" { Text "D:/实验室/pg_070731/cyclic.vhd" 233 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fran_pg fran_pg:pattern_generator " "Info: Elaborating entity \"fran_pg\" for hierarchy \"fran_pg:pattern_generator\"" {  } { { "cyclic.vhd" "pattern_generator" { Text "D:/实验室/pg_070731/cyclic.vhd" 244 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "moving_object fran_pg:pattern_generator\|moving_object:themoving_object " "Info: Elaborating entity \"moving_object\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\"" {  } { { "fran_pg.tdf" "themoving_object" { Text "D:/实验室/pg_070731/fran_pg.tdf" 130 1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "moving_object.vhd(279) " "Info: VHDL Case Statement information at moving_object.vhd(279): OTHERS choice is never selected" {  } { { "moving_object.vhd" "" { Text "D:/实验室/pg_070731/moving_object.vhd" 279 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "moving_object.vhd(373) " "Info: VHDL Case Statement information at moving_object.vhd(373): OTHERS choice is never selected" {  } { { "moving_object.vhd" "" { Text "D:/实验室/pg_070731/moving_object.vhd" 373 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "mov_ram_r.vhd 2 1 " "Info: Using design file mov_ram_r.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mov_ram_r-SYN " "Info: Found design unit 1: mov_ram_r-SYN" {  } { { "mov_ram_r.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_r.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 mov_ram_r " "Info: Found entity 1: mov_ram_r" {  } { { "mov_ram_r.vhd" "" { Text "D:/实验室/pg_070731/mov_ram_r.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mov_ram_r fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1 " "Info: Elaborating entity \"mov_ram_r\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\"" {  } { { "moving_object.vhd" "u1_1" { Text "D:/实验室/pg_070731/moving_object.vhd" 179 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt3pram " "Info: Found entity 1: alt3pram" {  } { { "alt3pram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 97 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\"" {  } { { "mov_ram_r.vhd" "alt3pram_component" { Text "D:/实验室/pg_070731/mov_ram_r.vhd" 102 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 164 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdpram fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1 " "Info: Elaborating entity \"altdpram\" for hierarchy \"fran_pg:pattern_generator\|moving_object:themoving_object\|mov_ram_r:u1_1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\"" {  } { { "alt3pram.tdf" "altdpram_component1" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 184 2 0 } }  } 0}