📄 altsyncram_tif1.tdf
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PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a9 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 1,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 1,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a10 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 2,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 2,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a11 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 3,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 3,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a12 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 4,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 4,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a13 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 5,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 5,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a14 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 6,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 6,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
ram_block1a15 : cyclone_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_CLEAR = "none",
PORT_A_ADDRESS_WIDTH = 12,
PORT_A_DATA_IN_CLEAR = "none",
PORT_A_DATA_WIDTH = 1,
PORT_A_FIRST_ADDRESS = 4096,
PORT_A_FIRST_BIT_NUMBER = 7,
PORT_A_LAST_ADDRESS = 8191,
PORT_A_LOGICAL_RAM_DEPTH = 8192,
PORT_A_LOGICAL_RAM_WIDTH = 8,
PORT_A_WRITE_ENABLE_CLEAR = "none",
PORT_B_ADDRESS_CLEAR = "none",
PORT_B_ADDRESS_CLOCK = "clock0",
PORT_B_ADDRESS_WIDTH = 12,
PORT_B_DATA_OUT_CLEAR = "none",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 1,
PORT_B_FIRST_ADDRESS = 4096,
PORT_B_FIRST_BIT_NUMBER = 7,
PORT_B_LAST_ADDRESS = 8191,
PORT_B_LOGICAL_RAM_DEPTH = 8192,
PORT_B_LOGICAL_RAM_WIDTH = 8,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
RAM_BLOCK_TYPE = "auto"
);
address_a_wire[12..0] : WIRE;
address_b_wire[12..0] : WIRE;
clocken0 : NODE;
clocken1 : NODE;
BEGIN
address_reg_b[].CLK = ( clock1, clock0);
address_reg_b[].D = ( address_reg_b[0..0].Q, address_b[12..12]);
address_reg_b[].ENA = ( clocken1, clocken0);
decode2.data[0..0] = address_a_wire[12..12];
decode2.enable = wren_a;
mux3.data[] = ( ram_block1a[15..0].portbdataout[0..0]);
mux3.sel[0..0] = address_reg_b[1..1].Q;
ram_block1a[15..0].clk0 = clock0;
ram_block1a[15..0].clk1 = clock1;
ram_block1a[0].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[1].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[2].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[3].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[4].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[5].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[6].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[7].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[8].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[9].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[10].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[11].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[12].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[13].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[14].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[15].portaaddr[] = ( address_a_wire[11..0]);
ram_block1a[0].portadatain[] = ( data_a[0..0]);
ram_block1a[1].portadatain[] = ( data_a[1..1]);
ram_block1a[2].portadatain[] = ( data_a[2..2]);
ram_block1a[3].portadatain[] = ( data_a[3..3]);
ram_block1a[4].portadatain[] = ( data_a[4..4]);
ram_block1a[5].portadatain[] = ( data_a[5..5]);
ram_block1a[6].portadatain[] = ( data_a[6..6]);
ram_block1a[7].portadatain[] = ( data_a[7..7]);
ram_block1a[8].portadatain[] = ( data_a[0..0]);
ram_block1a[9].portadatain[] = ( data_a[1..1]);
ram_block1a[10].portadatain[] = ( data_a[2..2]);
ram_block1a[11].portadatain[] = ( data_a[3..3]);
ram_block1a[12].portadatain[] = ( data_a[4..4]);
ram_block1a[13].portadatain[] = ( data_a[5..5]);
ram_block1a[14].portadatain[] = ( data_a[6..6]);
ram_block1a[15].portadatain[] = ( data_a[7..7]);
ram_block1a[0].portawe = decode2.eq[0..0];
ram_block1a[1].portawe = decode2.eq[0..0];
ram_block1a[2].portawe = decode2.eq[0..0];
ram_block1a[3].portawe = decode2.eq[0..0];
ram_block1a[4].portawe = decode2.eq[0..0];
ram_block1a[5].portawe = decode2.eq[0..0];
ram_block1a[6].portawe = decode2.eq[0..0];
ram_block1a[7].portawe = decode2.eq[0..0];
ram_block1a[8].portawe = decode2.eq[1..1];
ram_block1a[9].portawe = decode2.eq[1..1];
ram_block1a[10].portawe = decode2.eq[1..1];
ram_block1a[11].portawe = decode2.eq[1..1];
ram_block1a[12].portawe = decode2.eq[1..1];
ram_block1a[13].portawe = decode2.eq[1..1];
ram_block1a[14].portawe = decode2.eq[1..1];
ram_block1a[15].portawe = decode2.eq[1..1];
ram_block1a[0].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[1].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[2].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[3].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[4].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[5].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[6].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[7].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[8].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[9].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[10].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[11].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[12].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[13].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[14].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[15].portbaddr[] = ( address_b_wire[11..0]);
ram_block1a[15..0].portbrewe = B"1111111111111111";
address_a_wire[] = address_a[];
address_b_wire[] = address_b[];
clocken0 = VCC;
clocken1 = VCC;
q_b[] = mux3.result[];
END;
--VALID FILE
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