altsyncram_gga2.tdf

基于fpga的屏幕测试程序

			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a10 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a11 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a12 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a13 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a14 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block3a15 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "sinewave_rom.mif",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock0",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 4096,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 8192,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLEAR = "none",
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 4096,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 8191,
			PORT_B_LOGICAL_RAM_DEPTH = 8192,
			PORT_B_LOGICAL_RAM_WIDTH = 8,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR = "none",
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	clocken0	: NODE;
	clocken1	: NODE;
	data_a[7..0]	: NODE;
	wren_a	: NODE;

BEGIN 
	address_reg_a[].CLK = clock0;
	address_reg_a[].D = ( address_reg_a[0..0].Q, address_a[12..12]);
	address_reg_a[].ENA = ( clocken0, clocken0);
	address_reg_b[].CLK = clock1;
	address_reg_b[].D = address_b[12..12];
	address_reg_b[].ENA = clocken1;
	decode4.data[0..0] = address_a[12..12];
	decode4.enable = wren_a;
	decode5.data[0..0] = address_b[12..12];
	decode5.enable = wren_b;
	mux6.data[] = ( ram_block3a[15..0].portadataout[0..0]);
	mux6.sel[0..0] = address_reg_a[1..1].Q;
	mux7.data[] = ( ram_block3a[15..0].portbdataout[0..0]);
	mux7.sel[] = address_reg_b[].Q;
	ram_block3a[15..0].clk0 = clock0;
	ram_block3a[15..0].clk1 = clock1;
	ram_block3a[0].portaaddr[] = ( address_a[11..0]);
	ram_block3a[1].portaaddr[] = ( address_a[11..0]);
	ram_block3a[2].portaaddr[] = ( address_a[11..0]);
	ram_block3a[3].portaaddr[] = ( address_a[11..0]);
	ram_block3a[4].portaaddr[] = ( address_a[11..0]);
	ram_block3a[5].portaaddr[] = ( address_a[11..0]);
	ram_block3a[6].portaaddr[] = ( address_a[11..0]);
	ram_block3a[7].portaaddr[] = ( address_a[11..0]);
	ram_block3a[8].portaaddr[] = ( address_a[11..0]);
	ram_block3a[9].portaaddr[] = ( address_a[11..0]);
	ram_block3a[10].portaaddr[] = ( address_a[11..0]);
	ram_block3a[11].portaaddr[] = ( address_a[11..0]);
	ram_block3a[12].portaaddr[] = ( address_a[11..0]);
	ram_block3a[13].portaaddr[] = ( address_a[11..0]);
	ram_block3a[14].portaaddr[] = ( address_a[11..0]);
	ram_block3a[15].portaaddr[] = ( address_a[11..0]);
	ram_block3a[0].portadatain[] = ( data_a[0..0]);
	ram_block3a[1].portadatain[] = ( data_a[1..1]);
	ram_block3a[2].portadatain[] = ( data_a[2..2]);
	ram_block3a[3].portadatain[] = ( data_a[3..3]);
	ram_block3a[4].portadatain[] = ( data_a[4..4]);
	ram_block3a[5].portadatain[] = ( data_a[5..5]);
	ram_block3a[6].portadatain[] = ( data_a[6..6]);
	ram_block3a[7].portadatain[] = ( data_a[7..7]);
	ram_block3a[8].portadatain[] = ( data_a[0..0]);
	ram_block3a[9].portadatain[] = ( data_a[1..1]);
	ram_block3a[10].portadatain[] = ( data_a[2..2]);
	ram_block3a[11].portadatain[] = ( data_a[3..3]);
	ram_block3a[12].portadatain[] = ( data_a[4..4]);
	ram_block3a[13].portadatain[] = ( data_a[5..5]);
	ram_block3a[14].portadatain[] = ( data_a[6..6]);
	ram_block3a[15].portadatain[] = ( data_a[7..7]);
	ram_block3a[0].portawe = decode4.eq[0..0];
	ram_block3a[1].portawe = decode4.eq[0..0];
	ram_block3a[2].portawe = decode4.eq[0..0];
	ram_block3a[3].portawe = decode4.eq[0..0];
	ram_block3a[4].portawe = decode4.eq[0..0];
	ram_block3a[5].portawe = decode4.eq[0..0];
	ram_block3a[6].portawe = decode4.eq[0..0];
	ram_block3a[7].portawe = decode4.eq[0..0];
	ram_block3a[8].portawe = decode4.eq[1..1];
	ram_block3a[9].portawe = decode4.eq[1..1];
	ram_block3a[10].portawe = decode4.eq[1..1];
	ram_block3a[11].portawe = decode4.eq[1..1];
	ram_block3a[12].portawe = decode4.eq[1..1];
	ram_block3a[13].portawe = decode4.eq[1..1];
	ram_block3a[14].portawe = decode4.eq[1..1];
	ram_block3a[15].portawe = decode4.eq[1..1];
	ram_block3a[0].portbaddr[] = ( address_b[11..0]);
	ram_block3a[1].portbaddr[] = ( address_b[11..0]);
	ram_block3a[2].portbaddr[] = ( address_b[11..0]);
	ram_block3a[3].portbaddr[] = ( address_b[11..0]);
	ram_block3a[4].portbaddr[] = ( address_b[11..0]);
	ram_block3a[5].portbaddr[] = ( address_b[11..0]);
	ram_block3a[6].portbaddr[] = ( address_b[11..0]);
	ram_block3a[7].portbaddr[] = ( address_b[11..0]);
	ram_block3a[8].portbaddr[] = ( address_b[11..0]);
	ram_block3a[9].portbaddr[] = ( address_b[11..0]);
	ram_block3a[10].portbaddr[] = ( address_b[11..0]);
	ram_block3a[11].portbaddr[] = ( address_b[11..0]);
	ram_block3a[12].portbaddr[] = ( address_b[11..0]);
	ram_block3a[13].portbaddr[] = ( address_b[11..0]);
	ram_block3a[14].portbaddr[] = ( address_b[11..0]);
	ram_block3a[15].portbaddr[] = ( address_b[11..0]);
	ram_block3a[0].portbdatain[] = ( data_b[0..0]);
	ram_block3a[1].portbdatain[] = ( data_b[1..1]);
	ram_block3a[2].portbdatain[] = ( data_b[2..2]);
	ram_block3a[3].portbdatain[] = ( data_b[3..3]);
	ram_block3a[4].portbdatain[] = ( data_b[4..4]);
	ram_block3a[5].portbdatain[] = ( data_b[5..5]);
	ram_block3a[6].portbdatain[] = ( data_b[6..6]);
	ram_block3a[7].portbdatain[] = ( data_b[7..7]);
	ram_block3a[8].portbdatain[] = ( data_b[0..0]);
	ram_block3a[9].portbdatain[] = ( data_b[1..1]);
	ram_block3a[10].portbdatain[] = ( data_b[2..2]);
	ram_block3a[11].portbdatain[] = ( data_b[3..3]);
	ram_block3a[12].portbdatain[] = ( data_b[4..4]);
	ram_block3a[13].portbdatain[] = ( data_b[5..5]);
	ram_block3a[14].portbdatain[] = ( data_b[6..6]);
	ram_block3a[15].portbdatain[] = ( data_b[7..7]);
	ram_block3a[0].portbrewe = decode5.eq[0..0];
	ram_block3a[1].portbrewe = decode5.eq[0..0];
	ram_block3a[2].portbrewe = decode5.eq[0..0];
	ram_block3a[3].portbrewe = decode5.eq[0..0];
	ram_block3a[4].portbrewe = decode5.eq[0..0];
	ram_block3a[5].portbrewe = decode5.eq[0..0];
	ram_block3a[6].portbrewe = decode5.eq[0..0];
	ram_block3a[7].portbrewe = decode5.eq[0..0];
	ram_block3a[8].portbrewe = decode5.eq[1..1];
	ram_block3a[9].portbrewe = decode5.eq[1..1];
	ram_block3a[10].portbrewe = decode5.eq[1..1];
	ram_block3a[11].portbrewe = decode5.eq[1..1];
	ram_block3a[12].portbrewe = decode5.eq[1..1];
	ram_block3a[13].portbrewe = decode5.eq[1..1];
	ram_block3a[14].portbrewe = decode5.eq[1..1];
	ram_block3a[15].portbrewe = decode5.eq[1..1];
	clocken0 = VCC;
	clocken1 = VCC;
	data_a[] = VCC;
	q_a[] = mux6.result[];
	q_b[] = mux7.result[];
	wren_a = GND;
END;
--VALID FILE