mux_vab.tdf

基于fpga的屏幕测试程序

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_vab
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data236w[1..0]	: WIRE;
	w_data250w[1..0]	: WIRE;
	w_data262w[1..0]	: WIRE;
	w_data274w[1..0]	: WIRE;
	w_data286w[1..0]	: WIRE;
	w_data298w[1..0]	: WIRE;
	w_data310w[1..0]	: WIRE;
	w_data322w[1..0]	: WIRE;
	w_result237w	: WIRE;
	w_result243w	: WIRE;
	w_result251w	: WIRE;
	w_result257w	: WIRE;
	w_result263w	: WIRE;
	w_result269w	: WIRE;
	w_result275w	: WIRE;
	w_result281w	: WIRE;
	w_result287w	: WIRE;
	w_result293w	: WIRE;
	w_result299w	: WIRE;
	w_result305w	: WIRE;
	w_result311w	: WIRE;
	w_result317w	: WIRE;
	w_result323w	: WIRE;
	w_result329w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result323w, w_result311w, w_result299w, w_result287w, w_result275w, w_result263w, w_result251w, w_result237w);
	sel_node[] = ( sel[0..0]);
	w_data236w[] = ( data[8..8], data[0..0]);
	w_data250w[] = ( data[9..9], data[1..1]);
	w_data262w[] = ( data[10..10], data[2..2]);
	w_data274w[] = ( data[11..11], data[3..3]);
	w_data286w[] = ( data[12..12], data[4..4]);
	w_data298w[] = ( data[13..13], data[5..5]);
	w_data310w[] = ( data[14..14], data[6..6]);
	w_data322w[] = ( data[15..15], data[7..7]);
	w_result237w = w_result243w;
	w_result243w = ((sel_node[] & w_data236w[1..1]) # ((! sel_node[]) & w_data236w[0..0]));
	w_result251w = w_result257w;
	w_result257w = ((sel_node[] & w_data250w[1..1]) # ((! sel_node[]) & w_data250w[0..0]));
	w_result263w = w_result269w;
	w_result269w = ((sel_node[] & w_data262w[1..1]) # ((! sel_node[]) & w_data262w[0..0]));
	w_result275w = w_result281w;
	w_result281w = ((sel_node[] & w_data274w[1..1]) # ((! sel_node[]) & w_data274w[0..0]));
	w_result287w = w_result293w;
	w_result293w = ((sel_node[] & w_data286w[1..1]) # ((! sel_node[]) & w_data286w[0..0]));
	w_result299w = w_result305w;
	w_result305w = ((sel_node[] & w_data298w[1..1]) # ((! sel_node[]) & w_data298w[0..0]));
	w_result311w = w_result317w;
	w_result317w = ((sel_node[] & w_data310w[1..1]) # ((! sel_node[]) & w_data310w[0..0]));
	w_result323w = w_result329w;
	w_result329w = ((sel_node[] & w_data322w[1..1]) # ((! sel_node[]) & w_data322w[0..0]));
END;
--VALID FILE