sinewave.vhd

来自「基于fpga的屏幕测试程序」· VHDL 代码 · 共 316 行

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.all;
 
ENTITY sinewave IS

GENERIC
(	
	DST		: integer :=32;
	LBAR    : integer :=480;
	RBAR    : integer :=800;
	HWIDTH  : integer :=180;
	VWIDTH	: integer :=50	
);

PORT
(
	clk     		: IN STD_LOGIC;
	clken	 		: IN STD_LOGIC;
  	hcount  		: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
  	vcount  		: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	HAC				: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	VAC				: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	graymax			: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	graymin			: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
	ram_data		: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	ram_wraddress	: IN STD_LOGIC_VECTOR(8 DOWNTO 0);
	
	cycle			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	reverse			: IN STD_LOGIC;
	download		: IN STD_LOGIC;
	speed			: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	delay			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	distance		: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	
	red_out			: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	gre_out			: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	blu_out			: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);

END sinewave;

ARCHITECTURE rtl OF sinewave IS
SIGNAL nn			: integer RANGE 1023 DOWNTO 0 := 0;
SIGNAL dist			: integer RANGE 511 DOWNTO 0 ;
SIGNAL count		: integer RANGE 359 DOWNTO 0 ;
SIGNAL countmax		: integer RANGE 511 DOWNTO 0 ;
SIGNAL HCE 			: integer range 1023 downto 0 := 640;
SIGNAL VCE 			: integer range 1023 downto 0 := 512;
SIGNAL flag		    : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL GLmax		: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL GLmin		: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL ram_rdaddress_a  	: STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL tmp_rdaddress_a  	: STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL ram_qa 	    		: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL ram_rdaddress_b  	: STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL tmp_rdaddress_b  	: STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL ram_qb 	    		: STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL rom_address1  : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL main_address1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_address1  : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_ad_temp1  : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL q1 	   		 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL q_temp1	   : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL q_out1	   : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL rom_address2  : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL main_address2 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_address2  : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL sub_ad_temp2  : STD_LOGIC_VECTOR (10 DOWNTO 0);
SIGNAL q2		     : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL q_temp2	    : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL q_out2 	    : STD_LOGIC_VECTOR (7 DOWNTO 0);

SIGNAL storage_out		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL red_out_temp		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL gre_out_temp		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL blu_out_temp		: STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT buf_ram IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
	
COMPONENT sinewave_rom IS PORT
	(
		clock	: IN STD_LOGIC ;
		address	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT sinewave_rom2 IS PORT
	(
		clock	: IN STD_LOGIC ;
		address	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;
-------------------------------------------------------------	
BEGIN

w0: buf_ram PORT MAP
	(  
		data		=>	ram_data,
		wraddress	=>	ram_wraddress,
		rdaddress_a	=>	ram_rdaddress_a,
		rdaddress_b	=>	ram_rdaddress_b,
		wren		=>	'1',
		clock		=>	clk,
		qa			=>	ram_qa,
		qb			=>	ram_qb
	);

w1 : sinewave_rom PORT MAP
	(
		clock	=>	clk,
		address	=>	rom_address1,
		q		=>	q1
	);

w2 : sinewave_rom2 PORT MAP
	(
		clock	=>	clk,
		address	=>	rom_address2,
		q		=>	q2
	);

-------------------------------------------------------------

PROCESS(clk)
BEGIN
	IF clk'event AND clk='1' THEN
		HCE 		<= conv_integer(HAC(10 downto 1));
		VCE 		<= conv_integer(VAC(10 downto 1));
		countmax 	<= conv_integer(delay)*30;
		GLmax 		<= graymax(9 DOWNTO 2);
		GLmin  		<= graymin(9 DOWNTO 2);			
		main_address1 <= cycle;
		main_address2 <= cycle;
	END IF;
END PROCESS;

PROCESS(clk,distance)
BEGIN
IF clk'event AND clk='1' THEN
	CASE distance IS
		WHEN  "0000"=>	dist <= 0;
		WHEN  "0001"=>	dist <= DST*1;
		WHEN  "0010"=>	dist <= DST*2;
	    WHEN  "0011"=>	dist <= DST*3;
	    WHEN  "0100"=>	dist <= DST*4;
	    WHEN  "0101"=>	dist <= DST*5;
	    WHEN  "0110"=>	dist <= DST*6;
	    WHEN  "0111"=>	dist <= DST*7;
	    WHEN  "1000"=>	dist <= DST*8;
	    WHEN  "1001"=>	dist <= DST*9;
		WHEN  "1010"=>	dist <= DST*10;
		WHEN  "1011"=>	dist <= DST*11;
		WHEN  "1100"=>	dist <= DST*12;
		WHEN  "1101"=>	dist <= DST*13;
		WHEN  "1110"=>	dist <= DST*14;
		WHEN  "1111"=>	dist <= DST*15;
	    WHEN OTHERS =>	dist <= 0;
	END CASE;
END IF;	
END PROCESS;

PROCESS(clk)
BEGIN
	IF clk'event AND clk='1' THEN
		rom_address1 <= main_address1 & sub_address1(8 DOWNTO 0);
		q_temp1 <= (GLmax-GLmin)*q1;
		q_out1 <= GLmin + q_temp1(15 DOWNTO 8);
		
		rom_address2 <= main_address2 & sub_address2(8 DOWNTO 0);
		q_temp2 <= (GLmax-GLmin)*q2;
		q_out2 <= GLmin + q_temp2(15 DOWNTO 8);
		
		ram_rdaddress_a <=	tmp_rdaddress_a(8 DOWNTO 0);
		ram_rdaddress_b <=	tmp_rdaddress_b(8 DOWNTO 0);
	END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	IF clken='1' THEN   
		IF nn>=RBAR+dist THEN   
			if count=countmax then
				nn <= LBAR-dist;
				count <= 0;
			else 
				count <= count+1;
				nn <= RBAR+dist;
			end if;
		ELSE
			nn <= (nn+conv_integer(speed));
		END IF;
	END IF;
END IF;
END PROCESS;

PROCESS(clk,hcount,nn)
BEGIN
IF clk'event AND clk='1' THEN
	sub_ad_temp1 <= (hcount-nn);  
END IF;
END PROCESS; 

PROCESS(clk,sub_ad_temp1)
BEGIN
IF clk'event AND clk='1' THEN
	if  sub_ad_temp1<HWIDTH+HWIDTH then 
		sub_address1 <= sub_ad_temp1; 
	else 
		sub_address1 <= "00000000000";
	end if;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
	IF clk'event AND clk='1' THEN
		if hcount>=HCE-HWIDTH and hcount<HCE+HWIDTH
		 then
			sub_address2 	<= hcount-(HCE-HWIDTH);
			tmp_rdaddress_a <= hcount-(HCE-HWIDTH);
			tmp_rdaddress_b <= hcount-(HCE-HWIDTH);
		 else
			sub_address2 	<= "00000000000";
			tmp_rdaddress_a <= "00000000000";
			tmp_rdaddress_b <= "00000000000";			
		end if;
	END IF;
END PROCESS;

PROCESS(clk)
BEGIN
	IF clk'event AND clk='1' THEN
		if vcount>=VCE-VWIDTH+75 and vcount<=VCE+VWIDTH+75 and hcount>=LBAR-dist and hcount<RBAR+dist --and hcount>=nn and hcount<nn+HWIDTH+HWIDTH
		then
			 flag <= "0001";  -- motion object
		elsif vcount>=VCE-VWIDTH-75 and vcount<=VCE+VWIDTH-75 and hcount>=HCE-HWIDTH and hcount<HCE+HWIDTH
		then	 
			flag <= "0010";	  -- still object
		else
			flag <= "0100";	
		end if;
	END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	CASE download IS
		WHEN '0' =>
			storage_out	<=	q_out2;
		WHEN OTHERS =>
			storage_out	<=	ram_qa;
	END CASE;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	CASE flag IS
		WHEN "0001" =>		-- motion object
			red_out_temp	<=	q_out1;
			gre_out_temp	<=	q_out1;
			blu_out_temp	<=	q_out1;
		WHEN "0010" =>		-- still object
			red_out_temp	<=	storage_out;
			gre_out_temp	<=	storage_out;
			blu_out_temp	<=	storage_out;
		WHEN OTHERS =>
			red_out_temp	<=	"00000000";
			gre_out_temp	<=	"00000000";
			blu_out_temp	<=	"00000000";
	END CASE;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	CASE reverse IS
		WHEN '0' =>
			red_out	<=	red_out_temp;
			gre_out	<=	gre_out_temp;
			blu_out	<=	blu_out_temp;
		WHEN OTHERS =>
			red_out	<=	"11111111" - red_out_temp;
			gre_out	<=	"11111111" - gre_out_temp;
			blu_out	<=	"11111111" - blu_out_temp;
	END CASE;
END IF;
END PROCESS;

END rtl;