cyclic.vhd
来自「基于fpga的屏幕测试程序」· VHDL 代码 · 共 352 行
VHD
352 行
--LIBRARY altera_mf;
--USE altera_mf.altera_mf_components.all;
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
-------------------------------------------------------------------
entity cyclic is
port(
dclk : in std_logic;
clk1_in : in std_logic;
--clk2_in : in std_logic;
--clk3_in : in std_logic;
r_e_i : in std_logic_vector(9 downto 0);
g_e_i : in std_logic_vector(9 downto 0);
b_e_i : in std_logic_vector(9 downto 0);
de_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
r_e_o : out std_logic_vector(9 downto 0);
r_o_o : out std_logic_vector(9 downto 0);
g_e_o : out std_logic_vector(9 downto 0);
g_o_o : out std_logic_vector(9 downto 0);
b_e_o : out std_logic_vector(9 downto 0);
b_o_o : out std_logic_vector(9 downto 0);
clk_out1 : out std_logic;
de_out : out std_logic;
de_out_1 : out std_logic;
hsync_out : out std_logic;
hsync_out_1 : out std_logic;
vsync_out : out std_logic;
vsync_out_1 : out std_logic;
parity_out_o : out std_logic;
parity_out_e : out std_logic;
oei : out std_logic;
pdwni : out std_logic;
pixs_out : out std_logic;
pd_out : out std_logic;
--h_countout : out std_logic;
tp_in : in std_logic_vector(12 downto 1);
tp_out : out std_logic_vector(6 downto 1);
CPUGOo : out std_logic;
PDPGOo : out std_logic;
PDWNo : out std_logic;
--IRQ : in std_logic;
scl_pld : inout std_logic;
sda_pld : inout std_logic
);
end cyclic;
architecture rtl of cyclic is
SIGNAL lvds_dvi_sel : std_logic;
SIGNAL tp_sel : std_logic;
SIGNAL pixel_mode : std_logic;
SIGNAL clk1 : std_logic;
SIGNAL cnt : std_logic_vector(1 downto 0);
SIGNAL cnt_rst : std_logic;
--SIGNAL divider : std_logic; -- 0,clk_in ; 1,half clk_in
--SIGNAL clk1_buf_out : std_logic;
--SIGNAL clk1_buf1 : std_logic;
--SIGNAL clk1_buf2 : std_logic;
--SIGNAL clk1_buf3 : std_logic;
SIGNAL input_buf_r_e : std_logic_vector(9 downto 0);
SIGNAL input_buf_g_e : std_logic_vector(9 downto 0);
SIGNAL input_buf_b_e : std_logic_vector(9 downto 0);
SIGNAL input_buf_hsync : std_logic;
SIGNAL input_buf_vsync : std_logic;
SIGNAL input_buf_de : std_logic;
SIGNAL input_var : std_logic;
SIGNAL output_buf_r_e_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_g_e_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_b_e_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_r_o_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_g_o_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_b_o_dl : std_logic_vector(9 downto 0);
SIGNAL output_buf_hsync_dl : std_logic;
SIGNAL output_buf_vsync_dl : std_logic;
SIGNAL output_buf_de_dl : std_logic;
SIGNAL vsync_out_dl : std_logic;
SIGNAL hsync_out_dl : std_logic;
SIGNAL de_out_dl : std_logic;
SIGNAL r_e_o_dl : std_logic_vector(9 downto 0);
SIGNAL r_o_o_dl : std_logic_vector(9 downto 0);
SIGNAL g_e_o_dl : std_logic_vector(9 downto 0);
SIGNAL g_o_o_dl : std_logic_vector(9 downto 0);
SIGNAL b_e_o_dl : std_logic_vector(9 downto 0);
SIGNAL b_o_o_dl : std_logic_vector(9 downto 0);
SIGNAL corrected_r_e_i : std_logic_vector(9 downto 0);
-------------------------------------------------------------------
SIGNAL output_buf_r_e_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_g_e_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_b_e_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_r_o_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_g_o_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_b_o_pg : std_logic_vector(9 downto 0);
SIGNAL output_buf_hsync_pg : std_logic;
SIGNAL output_buf_vsync_pg : std_logic;
SIGNAL CPUGO_buf_pg : std_logic;
SIGNAL PDPGO_buf_pg : std_logic;
--SIGNAL IRQ_buf_pg : std_logic;
SIGNAL PWDN_buf_pg : std_logic;
SIGNAL PDWNO_buf_pg : std_logic;
SIGNAL parity_buf_pg : std_logic;
SIGNAL Rpatgen : std_logic_vector(9 downto 0);
SIGNAL Gpatgen : std_logic_vector(9 downto 0);
SIGNAL Bpatgen : std_logic_vector(9 downto 0);
SIGNAL output_buf_de_pg : std_logic;
SIGNAL vsync_out_pg : std_logic;
SIGNAL hsync_out_pg : std_logic;
SIGNAL de_out_pg : std_logic;
SIGNAL parity_out_pg : std_logic;
SIGNAL r_e_o_pg : std_logic_vector(9 downto 0);
SIGNAL r_o_o_pg : std_logic_vector(9 downto 0);
SIGNAL g_e_o_pg : std_logic_vector(9 downto 0);
SIGNAL g_o_o_pg : std_logic_vector(9 downto 0);
SIGNAL b_e_o_pg : std_logic_vector(9 downto 0);
SIGNAL b_o_o_pg : std_logic_vector(9 downto 0);
SIGNAL trigger_out_pg : std_logic;
SIGNAL expander_interface : std_logic_vector(7 downto 0);
component fran_pg
port(
Red_out : out std_logic_vector(9 downto 0);
Green_out : out std_logic_vector(9 downto 0);
Blue_out : out std_logic_vector(9 downto 0);
Xpander : in std_logic_vector(7 downto 0);
NBlank_out : out std_logic;
HSync_out : out std_logic;
VSync_out : out std_logic;
clk1 : in std_logic;
--IRQ : in std_logic;
CPUGO : out std_logic;
PDPGO : out std_logic;
PWDN : out std_logic;
parity_out : out std_logic;
--divider : out std_logic;
pixel_mode : out std_logic; -- 0,single ppf ; 1,double ppf
trigger_out : out std_logic;
lvds_dvi_sel : out std_logic
);
end component;
component expander
port(
SCL : in std_logic;
SDA : in std_logic;
expander_data_out : out std_logic_vector(7 downto 0);
clk1 : in std_logic
);
end component;
component rgb10to10
port(
lvds_dvi_sel : in std_logic;
Rpdp : in std_logic_vector(9 downto 0);
Gpdp : in std_logic_vector(9 downto 0);
Bpdp : in std_logic_vector(9 downto 0);
Rlcd : out std_logic_vector(9 downto 0);
Glcd : out std_logic_vector(9 downto 0);
Blcd : out std_logic_vector(9 downto 0)
);
end component;
----------------------------------------------------------------------------
BEGIN
clk1 <= clk1_in;
--DVI TO LVDS--------------------------------------------------------------
process(dclk)
begin
IF Rising_edge(dclk) THEN
corrected_r_e_i <= (input_buf_r_e(7) & input_buf_r_e(9 DOWNTO 8) & input_buf_r_e(6 DOWNTO 0));
input_buf_r_e <= r_e_i;
input_buf_g_e <= g_e_i;
input_buf_b_e <= b_e_i;
input_buf_hsync <= hsync_in;
input_buf_vsync <= vsync_in;
input_buf_de <= de_in;
output_buf_r_e_dl <= input_buf_r_e;
output_buf_g_e_dl <= input_buf_g_e;
output_buf_b_e_dl <= input_buf_b_e;
output_buf_r_o_dl <= input_buf_r_e;
output_buf_g_o_dl <= input_buf_g_e;
output_buf_b_o_dl <= input_buf_b_e;
output_buf_hsync_dl <= input_buf_hsync;
output_buf_vsync_dl <= input_buf_vsync;
output_buf_de_dl <= input_buf_de;
r_e_o_dl <=(output_buf_r_e_dl(7 downto 2) & output_buf_r_e_dl(9 downto 8) & output_buf_r_e_dl(1 DOWNTO 0));
r_o_o_dl <=(output_buf_r_o_dl(7 downto 2) & output_buf_r_o_dl(9 downto 8) & output_buf_r_o_dl(1 DOWNTO 0));
g_e_o_dl <=(output_buf_g_e_dl(7 downto 2) & output_buf_g_e_dl(9 downto 8) & output_buf_g_e_dl(1 DOWNTO 0));
g_o_o_dl <=(output_buf_g_o_dl(7 downto 2) & output_buf_g_o_dl(9 downto 8) & output_buf_g_o_dl(1 DOWNTO 0));
b_e_o_dl <=(output_buf_b_e_dl(7 downto 2) & output_buf_b_e_dl(9 downto 8) & output_buf_b_e_dl(1 DOWNTO 0));
b_o_o_dl <=(output_buf_b_o_dl(7 downto 2) & output_buf_b_o_dl(9 downto 8) & output_buf_b_o_dl(1 DOWNTO 0));
de_out_dl<= output_buf_de_dl;
hsync_out_dl <= output_buf_hsync_dl;
vsync_out_dl <= output_buf_vsync_dl;
END IF;
end process;
-------------------------------------------------------------------------------
i2c_expander : expander
PORT MAP (
SCL => scl_pld,
SDA => sda_pld,
expander_data_out => expander_interface,
clk1 => clk1
);
rgb10bitsconverter : rgb10to10 -- AvD, use this for PDP convention
PORT MAP (
lvds_dvi_sel => lvds_dvi_sel,
Rpdp => Rpatgen,
Gpdp => Gpatgen,
Bpdp => Bpatgen,
Rlcd => output_buf_r_e_pg,
Glcd => output_buf_g_e_pg,
Blcd => output_buf_b_e_pg
);
pattern_generator : fran_pg
PORT MAP (
lvds_dvi_sel => lvds_dvi_sel,
Red_out => Rpatgen,
Green_out => Gpatgen,
Blue_out => Bpatgen,
Xpander => expander_interface,
NBlank_out => output_buf_de_pg,
HSync_out => output_buf_hsync_pg,
VSync_out => output_buf_vsync_pg,
clk1 => clk1,
--divider => divider,
pixel_mode => pixel_mode,
CPUGO => CPUGO_buf_pg,
PDPGO => PDPGO_buf_pg,
--IRQ => IRQ_buf_pg,
PWDN => PDWNO_buf_pg,
trigger_out => trigger_out_pg,
parity_out => parity_buf_pg --? not present in Cyclic layout #1 !!
);
process(clk1)
begin
IF Rising_edge(clk1) THEN
r_e_o_pg <= output_buf_r_e_pg;
g_e_o_pg <= output_buf_g_e_pg;
b_e_o_pg <= output_buf_b_e_pg;
r_o_o_pg <= output_buf_r_e_pg;
g_o_o_pg <= output_buf_g_e_pg;
b_o_o_pg <= output_buf_b_e_pg;
hsync_out_pg <= output_buf_hsync_pg;
vsync_out_pg <= output_buf_vsync_pg;
de_out_pg <= output_buf_de_pg;
parity_out_pg <= parity_buf_pg;
END IF;
end process;
process(clk1)
begin
IF (Rising_edge(clk1)) THEN
oei <= '0'; --oei selects the LVDS input output enable: '1' for normal output, '0' for tri stated outputs
pd_out <= '1'; --pd_out selects the DVI. '1' = normal operation '0' = power down
pdwni <= '0'; --pdwni selects the LVDS input power down: '1' for normal output
pixs_out <= '0';--pixel_mode; --low level indicates 24 bits/clock for DVI, high = 48 bits/clock
CPUGOo <= '1';
PDPGOo <= '1';
PDWNo <= '1';
END IF;
end process;
process(tp_sel, clk1, dclk, de_out_dl, hsync_out_dl, vsync_out_dl,
r_e_o_dl, r_o_o_dl, g_e_o_dl, g_o_o_dl, b_e_o_dl, b_o_o_dl,
de_out_pg, hsync_out_pg, vsync_out_pg, parity_out_pg,
r_e_o_pg, r_o_o_pg, g_e_o_pg, g_o_o_pg, b_e_o_pg, b_o_o_pg)
begin
CASE tp_sel IS
WHEN '0' =>
clk_out1 <= clk1;
de_out <= de_out_pg;
de_out_1 <= de_out_pg;
hsync_out <= hsync_out_pg;
hsync_out_1 <= hsync_out_pg;
vsync_out <= vsync_out_pg;
vsync_out_1 <= vsync_out_pg;
parity_out_o<= parity_out_pg;
parity_out_e<= parity_out_pg;
r_e_o <= r_e_o_pg;
r_o_o <= r_o_o_pg;
g_e_o <= g_e_o_pg;
g_o_o <= g_o_o_pg;
b_e_o <= b_e_o_pg;
b_o_o <= b_o_o_pg;
WHEN '1' =>
clk_out1 <= dclk;
de_out <= de_out_dl;
de_out_1 <= de_out_dl;
hsync_out <= hsync_out_dl;
hsync_out_1 <= hsync_out_dl;
vsync_out <= vsync_out_dl;
vsync_out_1 <= vsync_out_dl;
parity_out_o<= parity_out_pg;
parity_out_e<= parity_out_pg;
r_e_o <= r_e_o_dl;
r_o_o <= r_o_o_dl;
g_e_o <= g_e_o_dl;
g_o_o <= g_o_o_dl;
b_e_o <= b_e_o_dl;
b_o_o <= b_o_o_dl;
END CASE ;
END process;
tp_sel <= tp_in(12) ;
tp_out(1) <= '0' ;
tp_out(3) <= '0' ;
tp_out(2) <= parity_out_pg ;
tp_out(4) <= trigger_out_pg ;
tp_out(5) <= '1' ;
tp_out(6) <= '0' ;
end rtl;
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