fran_pg.tdf

基于fpga的屏幕测试程序

thehmovingbar2.velocity[5..0]     = (fullregbuf[118],fullregbuf[116..112]);

thehbar2.clk                = klok;
thehbar2.VAC[]          	= VAC[];
thehbar2.blocksize[6..0]    = fullregbuf[111..105];
thehbar2.v_sta[]		  	= theblocksize_2.vsta[];
thehbar2.v_end[]		  	= theblocksize_2.vend[];
thehbar2.act_vcounter[]     = act_vcounter.q[];
thehbar2.vposition[10..0]   = (fullregbuf[104],0,0,fullregbuf[103..98],0,0);

-------------------------------------------------------------------------------
-- BLOCK + V MOVINGBLOCK -------------------------------------------------------
-------------------------------------------------------------------------------
thevmovingbar1.clk                = klok;
thevmovingbar1.VAC[]              = VAC[];
thevmovingbar1.vout_pulse         = vout_pulse;
thevmovingbar1.act_vcounter[]     = act_vcounter.q[];
thevmovingbar1.blocksize[]        = fullregbuf[69..63];
thevmovingbar1.v_sta[]			  = theblocksize_1.vsta[];
thevmovingbar1.v_end[]			  = theblocksize_1.vend[];
thevmovingbar1.velocity[5..0]     = (fullregbuf[76],fullregbuf[74..70]);

thevmovingbar2.clk                = klok;
thevmovingbar2.VAC[]              = VAC[];
thevmovingbar2.vout_pulse         = vout_pulse;
thevmovingbar2.act_vcounter[]     = act_vcounter.q[];
thevmovingbar2.blocksize[]        = fullregbuf[111..105];
thevmovingbar2.v_sta[]			  = theblocksize_2.vsta[];
thevmovingbar2.v_end[]			  = theblocksize_2.vend[];
thevmovingbar2.velocity[5..0]     = (fullregbuf[118],fullregbuf[116..112]);

thevbar1.clk                = klok;
thevbar1.HAC[]          	= HAC[];
thevbar1.blocksize[6..0]    = fullregbuf[69..63];
thevbar1.h_sta[11..0]     	= theblocksize_1.hsta[];
thevbar1.h_end[11..0]    	= theblocksize_1.hend[];
thevbar1.act_hcounter[]     = act_hcounter.q[];
thevbar1.hposition[10..0]   = (fullregbuf[62],0,fullregbuf[61..56],0,0,0);

-------------------------------------------------------------------------------
-- rgb ramps section ----------------------------------------------------------
-------------------------------------------------------------------------------
thergbramp.clk 				   = klok;
thergbramp.VPS_0[] 			   = VPS_0[];
thergbramp.VPS_1[] 			   = VPS_1[];
thergbramp.VPS_2[] 			   = VPS_2[];
thergbramp.VPS_3[] 			   = VPS_3[];
thergbramp.act_vcounter[10..0] = act_vcounter.q[10..0];
thergbramp.act_hcounter[10..0] = act_hcounter.q[10..0];

-------------------------------------------------------------------------------
-- blocksize section-----------------------------------------------------------
-------------------------------------------------------------------------------
theblocksize_1.clk			= klok;
theblocksize_2.clk			= klok;
theblocksize_3.clk			= klok;
theblocksize_1.sel[3..0]	= res_sel[3..0];
theblocksize_2.sel[3..0]	= res_sel[3..0];
theblocksize_3.sel[3..0]	= res_sel[3..0];
theblocksize_1.size[]		= fullregbuf[69..63];
theblocksize_2.size[]		= fullregbuf[111..105];
theblocksize_3.size[]		= fullregbuf[20..14];
theblocksize_1.pixel_mode	= pixel_mode;
theblocksize_2.pixel_mode	= pixel_mode;
theblocksize_3.pixel_mode	= pixel_mode;

-------------------------------------------------------------------------------
-- blockseries 3L section------------------------------------------------------
-------------------------------------------------------------------------------
theserial_3L.clk			= klok;
theserial_3L.clk_en			= start_v_pulse;
theserial_3L.reset			= fullregbuf[153];

theserial_3L.time0[]		= 6;
theserial_3L.time1[]		= (0,fullregbuf[160..154]);
theserial_3L.time2[]		= (0,fullregbuf[167..161]);
theserial_3L.time3[]		= (0,fullregbuf[174..168]);

theserial_3L.red_in0[]   	= (fullregbuf[28..21],fullregbuf[50..49]);
theserial_3L.green_in0[] 	= (fullregbuf[36..29],fullregbuf[52..51]);
theserial_3L.blue_in0[]  	= (fullregbuf[44..37],fullregbuf[54..53]);

theserial_3L.red_in1[]   	= (fullregbuf[63..56],fullregbuf[129..128]);
theserial_3L.green_in1[] 	= (fullregbuf[71..64],fullregbuf[131..130]);
theserial_3L.blue_in1[]  	= (fullregbuf[79..72],fullregbuf[133..132]);

theserial_3L.red_in2[]   	= (fullregbuf[87..80],fullregbuf[135..134]);
theserial_3L.green_in2[] 	= (fullregbuf[95..88],fullregbuf[137..136]);
theserial_3L.blue_in2[]  	= (fullregbuf[103..96],fullregbuf[139..138]);

--trigger_out					= theserial_3L.trigger_out;
-------------------------------------------------------------------------------
-- blockseries 5L section---------------------------------------------------------
-------------------------------------------------------------------------------
theserial.clk			= klok;
theserial.clk_en		= start_v_pulse;
theserial.reset			= fullregbuf[153];

theserial.time0[]		= 6;
theserial.time1[]		= (0,fullregbuf[160..154]);
theserial.time2[]		= (0,fullregbuf[167..161]);
theserial.time3[]		= (0,fullregbuf[174..168]);
theserial.time4[]		= (0,fullregbuf[181..175]);
theserial.time5[]		= (0,fullregbuf[188..182]);

theserial.red_in0[]   	= (fullregbuf[28..21],fullregbuf[50..49]);
theserial.green_in0[] 	= (fullregbuf[36..29],fullregbuf[52..51]);
theserial.blue_in0[]  	= (fullregbuf[44..37],fullregbuf[54..53]);

theserial.red_in1[]   	= (fullregbuf[63..56],fullregbuf[129..128]);
theserial.green_in1[] 	= (fullregbuf[71..64],fullregbuf[131..130]);
theserial.blue_in1[]  	= (fullregbuf[79..72],fullregbuf[133..132]);

theserial.red_in2[]   	= (fullregbuf[87..80],fullregbuf[135..134]);
theserial.green_in2[] 	= (fullregbuf[95..88],fullregbuf[137..136]);
theserial.blue_in2[]  	= (fullregbuf[103..96],fullregbuf[139..138]);

theserial.red_in3[]   	= (fullregbuf[111..104],fullregbuf[141..140]);
theserial.green_in3[] 	= (fullregbuf[119..112],fullregbuf[143..142]);
theserial.blue_in3[]  	= (fullregbuf[127..120],fullregbuf[145..144]);

theserial.red_in4[]   	= (fullregbuf[196..189],fullregbuf[214..213]);
theserial.green_in4[] 	= (fullregbuf[204..197],fullregbuf[216..215]);
theserial.blue_in4[]  	= (fullregbuf[212..205],fullregbuf[218..217]);

trigger_out				= theserial.trigger_out;

-------------------------------------------------------------------------------
-- nine blocks ----------------------------------------------------------------
-------------------------------------------------------------------------------
thehbar3.clk                = klok;
thehbar3.VAC[]          	= VAC[];
thehbar3.blocksize[6..0]    = fullregbuf[20..14];
thehbar3.v_sta[]			= theblocksize_3.vsta[];
thehbar3.v_end[]			= theblocksize_3.vend[];
thehbar3.act_vcounter[]     = act_vcounter.q[];
thehbar3.vposition[10..0]   = VP1[];

thehbar4.clk                = klok;
thehbar4.VAC[]          	= VAC[];
thehbar4.blocksize[6..0]    = fullregbuf[20..14];
thehbar4.v_sta[]			= theblocksize_3.vsta[];
thehbar4.v_end[]			= theblocksize_3.vend[];
thehbar4.act_vcounter[]     = act_vcounter.q[];
thehbar4.vposition[10..0]   = VP2[];

thehbar5.clk                = klok;
thehbar5.VAC[]          	= VAC[];
thehbar5.blocksize[6..0]    = fullregbuf[20..14];
thehbar5.v_sta[]			= theblocksize_3.vsta[];
thehbar5.v_end[]			= theblocksize_3.vend[];
thehbar5.act_vcounter[]     = act_vcounter.q[];
thehbar5.vposition[10..0]   = VP3[];

thevbar3.clk                = klok;
thevbar3.HAC[]          	= HAC[];
thevbar3.blocksize[6..0]    = fullregbuf[20..14];
thevbar3.h_sta[]			= theblocksize_3.hsta[];
thevbar3.h_end[]			= theblocksize_3.hend[];
thevbar3.act_hcounter[]     = act_hcounter.q[];
thevbar3.hposition[10..0]   = HP1[];

thevbar4.clk                = klok;
thevbar4.HAC[]          	= HAC[];
thevbar4.blocksize[6..0]    = fullregbuf[20..14];
thevbar4.h_sta[]			= theblocksize_3.hsta[];
thevbar4.h_end[]			= theblocksize_3.hend[];
thevbar4.act_hcounter[]     = act_hcounter.q[];
thevbar4.hposition[10..0]   = HP2[];

thevbar5.clk                = klok;
thevbar5.HAC[]          	= HAC[];
thevbar5.blocksize[6..0]    = fullregbuf[20..14];
thevbar5.h_sta[]			= theblocksize_3.hsta[];
thevbar5.h_end[]			= theblocksize_3.hend[];
thevbar5.act_hcounter[]     = act_hcounter.q[];
thevbar5.hposition[10..0]   = HP3[];

-------------------------------------------------------------------------------
-- simulation: for perception study -------------------------------------------
-------------------------------------------------------------------------------
themoving_object.clk 			 = klok;
themoving_object.vcount[10..0] 	 = act_vcounter.q[10..0];
themoving_object.hcount[10..0] 	 = act_hcounter.q[10..0];
themoving_object.clken  		 = start_v_pulse;
themoving_object.wren 			 = fullregbuf[45]; 		--ram write enalbe
themoving_object.reverse 		 = fullregbuf[46]; 		--swap grayscales of back and front 
themoving_object.speed[5..0]	 = fullregbuf[52..47]; 	-- motion speed
themoving_object.back_red[7..0]  = fullregbuf[28..21];
themoving_object.back_gre[7..0]  = fullregbuf[36..29];
themoving_object.back_blu[7..0]  = fullregbuf[44..37];
themoving_object.front_red[7..0] = fullregbuf[63..56];
themoving_object.front_gre[7..0] = fullregbuf[71..64];
themoving_object.front_blu[7..0] = fullregbuf[79..72];
themoving_object.delay[3..0] 	 = fullregbuf[83..80];  --disappear time of moving object
themoving_object.bar[3..0] 		 = fullregbuf[87..84];  --bar grayscale
themoving_object.address[8..0] 	 = fullregbuf[96..88];  --address of simulation object
themoving_object.date_r[7..0] 	 = fullregbuf[104..97]; --data, with address down from i2c by labview
themoving_object.date_g[7..0] 	 = fullregbuf[112..105];
themoving_object.date_b[7..0] 	 = fullregbuf[120..113];
themoving_object.distance[3..0]  = fullregbuf[124..121]; --moving distance select 

-------------------------------------------------------------------------------
-- pattern_dl: sine curves measurement ----------------------------------------
------------------------------------------------------------------------------- 
thepattern_dl.clk		    	= klok;
thepattern_dl.clken		    	= start_v_pulse;
thepattern_dl.wren 			 	= fullregbuf[45]; --ram write enalbe
thepattern_dl.hcount[10..0]		= act_hcounter.q[10..0]; 
thepattern_dl.vcount[10..0]		= act_vcounter.q[10..0];
thepattern_dl.data_length[13..0]= fullregbuf[76..63];
thepattern_dl.address[8..0] 	= fullregbuf[96..88];
thepattern_dl.date_r[7..0] 	 	= fullregbuf[104..97]; 
thepattern_dl.date_g[7..0] 	 	= fullregbuf[112..105];
thepattern_dl.date_b[7..0] 	 	= fullregbuf[120..113];

-------------------------------------------------------------------------------
-- sinewave: for perception ---------------------------------------------------
-------------------------------------------------------------------------------
%
thesinewave.clk			    =	klok;
thesinewave.clken		    =	start_v_pulse;
thesinewave.hcount[10..0]	=	act_hcounter.q[10..0]; 
thesinewave.vcount[10..0]	=	act_vcounter.q[10..0];
thesinewave.HAC[10..0]		=	HAC[10..0];
thesinewave.VAC[10..0]		=	VAC[10..0];
thesinewave.graymax[9..0]	=	(fullregbuf[28..21],0,0);	
thesinewave.graymin[9..0]	=	(fullregbuf[36..29],0,0);	
thesinewave.cycle[3..0]		=	fullregbuf[87..84];			
thesinewave.reverse			=	GND;--fullregbuf[72];
thesinewave.download		=	fullregbuf[46];
thesinewave.speed[5..0]	 	= 	fullregbuf[52..47]; 		
thesinewave.delay[3..0] 	= 	fullregbuf[83..80];   --disappear time 
thesinewave.distance[3..0]  = 	fullregbuf[107..104]; --select move distance
thesinewave.ram_data[7..0] 		 = fullregbuf[71..64];
thesinewave.ram_wraddress[8..0] = fullregbuf[96..88];
%



----------------------------------------
--IOexpander section--------------------
----------------------------------------
fullreg.clock = klok;                 --fullreg : importN7bits;
fullreg.data[7..0] = Xpander[7..0];   --Xpander[7..0]: INPUT;
                                      
fullregbuf[].clk = klok;              --buffering this with the vertical sync
fullregbuf[].d = fullreg.Xout[];	  --fullregbuf[216..0] : DFFE;
fullregbuf[].ena = vout_pulse;

-----------------------------------------
--Refresh Frequency select---------------
-----------------------------------------
--clk_sel_out[1..0]	=	clk_sel[1..0];

CASE freq_sel[2..0] IS             
  WHEN 0 => 
	H_sync_temp_count[11..0] = HTOT50[];
	V_sync_temp_count[10..0] = VTOT50[];
	--clk_sel[1..0] = 1;
  WHEN 1 => 
	H_sync_temp_count[11..0] = HTOT60[];
	V_sync_temp_count[10..0] = VTOT60[];
	--clk_sel[1..0] = 0;
  WHEN 2 => 
	H_sync_temp_count[11..0] = HTOT75[];
	V_sync_temp_count[10..0] = VTOT75[];
	--clk_sel[1..0] = 0;
  WHEN 3 => 
	H_sync_temp_count[11..0] = HTOT90[];
	V_sync_temp_count[10..0] = VTOT90[];
	--clk_sel[1..0] = 0;
  WHEN 4 => 
	H_sync_temp_count[11..0] = HTOT100[];
	V_sync_temp_count[10..0] = VTOT100[];
	--clk_sel[1..0] = 0;
  WHEN 5 => 
	H_sync_temp_count[11..0] = HTOT120[];
	V_sync_temp_count[10..0] = VTOT120[];
	--clk_sel[1..0] = 0;
  WHEN OTHERS => 
	H_sync_temp_count[11..0] = HTOT60[];
	V_sync_temp_count[10..0] = VTOT60[];
	--clk_sel[1..0] = 0;
END CASE;

-----------------------------------------------
--Horizontal Sync signal and counter section---
-----------------------------------------------
H_sync_end_count[11..0] = H_sync_temp_count[11..0];

h_counter.sclr  = start_h.aeb;
h_counter.clock = klok;

start_h.dataa[11..0] = (0,h_counter.q[10..0]);
start_h.datab[11..0] = H_sync_end_count[11..0] - 3;  --equals (HTOT - 3)
start_h.clock = klok;

end_h.dataa[11..0] = (0,h_counter.q[10..0]);
end_h.datab[11..0] = (0,HSY[]) - 3;
end_h.clock = klok;

hsync_art.clk = klok;
hsync_art.R = start_h.aeb;
hsync_art.S = end_h.aeb;

HSync_out	=	hsync_art.q;
--------------------------------------------
--H BLANK-----------------------------------
--------------------------------------------
start_n.dataa[10..0] = h_counter.q[10..0];
start_n.datab[10..0] = HSY[] - 3 + HBP[] - 4;
start_n.clock = klok;

end_n.dataa[10..0] = h_counter.q[10..0];
end_n.datab[10..0] = HSY[] - 3 + HBP[] - 4 + HAC[];
end_n.clock = klok;

nblank_art.clk = klok;
nblank_art.s = start_n.aeb and nblankv_art.q;  --nblankv_art is generated below
nblank_art.r = end_n.aeb;

nblank_art_delay[].clk = klok;
nblank_art_delay1.d = nblank_art.q;
nblank_art_delay2.d = nblank_art_delay1.q;
nblank_art_delay3.d = nblank_art_delay2.q;
nblank_art_delay4.d = nblank_art_delay3.q;

NBlank_out = nblank_art_delay4.q;

-------------------------------------------------
--Vertical Sync signal and counter section-------
-------------------------------------------------
V_sync_end_count[10..0] = V_sync_temp_count[10..0];

v_counter.sclr    = start_v.ageb;
v_counter.clk_en  = start_h.aeb;

v_counter.clock = klok;

start_v.dataa[10..0] = v_counter.q[10..0];
start_v.datab[10..0] = V_sync_end_count[10..0];
start_v.clock = klok;

end_v.dataa[10..0] = v_counter.q[10..0];
end_v.datab[10..0] = VSY[];
end_v.clock = klok;

vsync_art.clk = klok;
vsync_art.r = start_v.aeb;
vsync_art.s = end_v.aeb;

VSync_out =	vsync_art.q;

------------------------------------------
--V nBLANK--------------------------------
------------------------------------------
start_vn.dataa[10..0] = v_counter.q[10..0];
start_vn.datab[10..0] = VSY[] + VBP[];
start_vn.clock = klok;

end_vn.dataa[10..0] = v_counter.q[10..0];
end_vn.datab[10..0] = VSY[] + VBP[] + VAC[];
end_vn.clock = klok;

nblankv_art.clk = klok;
nblankv_art.s = start_vn.aeb;
nblankv_art.r = end_vn.aeb; --OR start_v.aeb;  ---- AvD, is OR part necessary?
-- nblankv_art.q is used above 

-----------------------------------------
-- ACTIVE h & v counters ----------------
-----------------------------------------
--AvD 
act_hcounter.sclr = NOT (nblank_art.q);
--act_hcounter.sclr = NOT (nblank_art_delay2.q);
act_hcounter.clock = klok;
-------------
act_vcounter.sclr = NOT (nblankv_art.q);
act_vcounter.clk_en  = start_h.aeb;
act_vcounter.clock = klok;
-------------

-- pulse at start of vsync:	positive pulse width is one klok cycle
start_v_delay.d = start_v.aeb;
start_v_delay.clk = klok;
start_v_pulse = (start_v.aeb AND NOT(start_v_delay.q));

-- pulse at end of vsync:
vout_delay.d = vsync_art.q;
vout_delay.clk = klok;
vout_pulse = (vsync_art.q AND NOT(vout_delay.q));

-- pulse at start of active video (used for crosshatch):
nblankv_art_delay.d = nblankv_art.q;
nblankv_art_delay.clk = klok;
start_nv_pulse = (nblankv_art.q AND NOT(nblankv_art_delay.q));

----------------------------
--PDP control sectiion -----
----------------------------
CPUGO	= VCC;
PDPGO	= VCC;
PWDN	= VCC;
DE_out  = VCC;

-----------------------------
-- field counting -----------
-----------------------------
--field_counter.clock = klok;
--field_counter.clk_en = start_v_pulse;
--mf_trigger_out = NOT(vsync_art.q) AND (level_counter.q==0) AND (field_counter.q==0);

%
CASE fullregbuf[11] IS
WHEN 0 =>
          mask=VCC;
WHEN 1 =>
          mask=(NOT field_counter.q0) AND (NOT field_counter.q1);
END CASE;
%

-------------------------------
--parity out-------------------
-------------------------------
CASE parity_sel[1..0] IS
WHEN 1 =>
  parity_out = GND;
WHEN 2 =>
  parity_out = VCC;
WHEN 0 =>
  parity_out = par_jk.q;
WHEN 3 =>
  parity_out = NOT(par_jk.q);
END CASE;

par_jk.J = VCC;
par_jk.K = VCC;
par_jk.clk = vsync_art.q;


END;