fran_pg.tdf

基于fpga的屏幕测试程序

TITLE "pattern generator for LCD & PDP measurement";

--For the LCD & PDP measurement
--Chai Lin
--08-27-2006

--referred from
--Yuning Zhang : for PDP measurement,2005
--Eric Funke (EF): original design
--Age van Dalfsen (AvD): reworked 
--AvD 2003-12-03

%
-------------------------------------------------------------------------------
The parameters of patterns are in a V-synchronised buffer (through I2C)
"fullregbuf[I2CBit..0]":

filled by one 8-bits expander, which receives the following format:

first byte
7	6	5	4	3	2	1	0
1	[		"address"		]

second byte
7	6	5	4	3	2	1	0
0	[		"data"			]
-------------------------------------------------------------------------------

fullregbuf[0]             8/10bits
8/10bits  0/1

fullregbuf[4..1]           pattern select
                          0       R=G=B=0
                          1       Central Block
						  3		  Variable Block
						  12	  One Shinning Block
                          13      Nine Shinning Blocks
                          14      pattern.dl

(fullregbuf[10],fullregbuf[6..5])      frame frequency
000 	50Hz
001 	60Hz
010 	75Hz
011 	90Hz
100 	100Hz
101 	120Hz

fullregbuf[9 . . 7]       RGB ON
           B  G  R


fullregbuf[11]           

fullregbuf[13..12]        parity-setting 00, 0101
                                         01, 0000
                                         10, 1111
                                         11, 1010

fullregbuf[20..14]        load area percentage
                          0  --100 (0,1,2,...,100)
                          101--120 (0.25,0.50,0.75,...,5.0)

%

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
include "fran_pg.inc";
include "importN7bits.inc"; 
include "rgbramps.inc";
include "varloadblocks.inc";
include "certaingrayscales.inc";
include "serials.inc";
include "serials_3L.inc";  
include "hmovingbars.inc";
include "vmovingbars.inc";
include "hbars.inc";
include "vbars.inc";
--include "sinewave.inc";
include "moving_object.inc";
include "pattern_dl.inc";
--include "blocksize.inc";
 
include "lpm_counter.inc";
include "lpm_compare.inc";
include "lpm_rom.inc";
include "lpm_add_sub.inc";

FUNCTION blocksize 
(	 clk,
	 sel[3..0],
	 pixel_mode,
	 size[6..0]
) 
RETURNS 
(	 vsta[11..0],
	 vend[11..0],
	 hsta[11..0],
	 hend[11..0]
);

SUBDESIGN fran_pg
(
clk1					: INPUT;
--IRQ 					: INPUT;
Xpander[7..0]			: INPUT;

Red_out[9..0]			: OUTPUT;
Green_out[9..0]			: OUTPUT;
Blue_out[9..0]			: OUTPUT;

Hsync_out   			: OUTPUT;
Vsync_out	    		: OUTPUT;
NBlank_out		    	: OUTPUT;
DE_out                  : OUTPUT;

CPUGO					: OUTPUT;
PDPGO					: OUTPUT;
PWDN					: OUTPUT;

pixel_mode				: OUTPUT;
parity_out              : OUTPUT;
trigger_out             : OUTPUT;
lvds_dvi_sel			: OUTPUT;
--clk_sel_out[1..0]		: OUTPUT;
)


VARIABLE
themoving_object		: moving_object;
--thesinewave				: sinewave;
thepattern_dl			: pattern_dl;
theblocksize_1			: blocksize;
theblocksize_2			: blocksize;
theblocksize_3			: blocksize;
thevarloadblock     	: varloadblocks;
thergbramp				: rgbramps;
theCertainGrayscale   	: CertainGrayscales;
theCertainGrayscale1   	: CertainGrayscales;
theCertainGrayscale2   	: CertainGrayscales;		
theserial          		: serials;
theserial_3L          	: serials_3L;

fullreg 				: importN7bits;
thehmovingbar1          : hmovingbars;
thehmovingbar2          : hmovingbars;
thevmovingbar1          : vmovingbars;
thevmovingbar2          : vmovingbars;
thehbar1 				: hbars;
thehbar2 				: hbars;         
thehbar3 				: hbars;
thehbar4 				: hbars;
thehbar5                : hbars;
thevbar1 				: vbars;
thevbar2 				: vbars;       
thevbar3 				: vbars;
thevbar4 				: vbars;
thevbar5 				: vbars;

fullregbuf[I2CBit..0]	: DFFE;
Red_on					: DFF;
Gre_on					: DFF;
Blu_on					: DFF;
Red_art[9..0]			: DFF;
Gre_art[9..0]	 		: DFF;
Blu_art[9..0]			: DFF;
hsync_art				: SRFF;
vsync_art				: SRFF;
vout_delay				: DFF;
nblankv_art 			: SRFF;
nblank_art				: SRFF;
nblank_art_delay[4..1]	: DFF;
nblankv_art_delay		: DFF;
start_v_delay           : DFF;
par_jk					: JKFF;

klok					: NODE;
res_sel[3..0]   		: NODE;
--clk_sel[1..0]			: NODE;
pattern[3..0]			: NODE;
Red_pat[9..0]			: NODE;
Gre_pat[9..0]			: NODE;
Blu_pat[9..0]			: NODE;
Renab					: NODE;
Genab					: NODE;
Benab					: NODE;

--mask                  : NODE;
start_v_pulse			: NODE;
vout_pulse				: NODE;
start_nv_pulse			: NODE;
H_sync_temp_count[11..0]: NODE;
H_sync_end_count[11..0] : NODE;
V_sync_temp_count[10..0]: NODE;
V_sync_end_count[10..0] : NODE;

HAC[10..0]  			: NODE;     
HSY[10..0]   			: NODE;     
HBP[10..0]   			: NODE;     
HTOT50[11..0] 			: NODE;     
HTOT60[11..0] 			: NODE;     
HTOT75[11..0] 			: NODE;      
HTOT90[11..0] 			: NODE;     
HTOT100[11..0] 			: NODE;     
HTOT120[11..0] 			: NODE;
--HTOT[11..0]				: NODE;

VAC[10..0]  			: NODE;     
VSY[10..0]   			: NODE;     
VBP[10..0]   			: NODE;
VTOT50[10..0] 			: NODE;
VTOT60[10..0] 			: NODE;      
VTOT75[10..0] 			: NODE;
VTOT90[10..0] 			: NODE;     
VTOT100[10..0] 			: NODE;     
VTOT120[10..0] 			: NODE;
--VTOT[10..0]				: NODE;

VPS_0[10..0] 			: NODE;     
VPS_1[10..0] 			: NODE;
VPS_2[10..0] 			: NODE;
VPS_3[10..0] 			: NODE;
HP1[10..0]  			: NODE;  
HP2[10..0]  			: NODE; 
HP3[10..0]  			: NODE;
VP1[10..0]  			: NODE;
VP2[10..0]  			: NODE;
VP3[10..0]  			: NODE;

freq_sel[2..0]			: NODE;
parity_sel[1..0]		: NODE;

start_h,  end_h,
start_v,  end_v,
start_n,  end_n,
start_vn, end_vn
     					: lpm_compare WITH (
									LPM_WIDTH = 12,
									ONE_INPUT_IS_CONSTANT = "YES",
									LPM_REPRESENTATION = "UNSIGNED",
									LPM_PIPELINE = 2
									);
																	
v_counter, 
h_counter,
act_hcounter,
act_vcounter			: lpm_counter WITH (
									LPM_WIDTH = 11,
									--LPM_MODULUS = ,
									LPM_DIRECTION = "UP"
									);

BEGIN
klok				= GLOBAL(clk1);

pixel_mode			= fullregbuf[146];
lvds_dvi_sel    	= fullregbuf[11];  -- 0:dvi interface, 1:lvds interface
res_sel[3..0] 		= fullregbuf[150..147];
freq_sel[2..0]		= (fullregbuf[10],fullregbuf[6..5]);
parity_sel[1..0]	= fullregbuf[13..12];
pattern[3..0] 		= fullregbuf[4..1];

%
-- testing ports
pixel_mode		= GND;
lvds_dvi_sel    	= GND;
res_sel[3..0] 	= B"0011";
freq_sel[2..0]	= B"001";
parity_sel[1..0]	= B"00";
pattern[3..0] 	= B"1110";
%
------------------------------------------------------------------------------
------ select timing parameters ----------------------------------------------
------------------------------------------------------------------------------

CASE res_sel[3..0] IS
WHEN 0 =>                  -- 1280 x 768
	HAC[10..0]     = HAC_WXGA;
	VAC[10..0]     = VAC_WXGA; 
	
	VPS_0[10..0] = VPS_0_WXGA;   
	VPS_1[10..0] = VPS_1_WXGA;
	VPS_2[10..0] = VPS_2_WXGA;
	VPS_3[10..0] = VPS_3_WXGA;

	HP1[10..0] = HP1_WXGA; 
	HP2[10..0] = HP2_WXGA;   
	HP3[10..0] = HP3_WXGA;  
	VP1[10..0] = VP1_WXGA;  
	VP2[10..0] = VP2_WXGA; 
	VP3[10..0] = VP3_WXGA; 
	
	HSY[10..0]     = HSY_WXGA;
	HBP[10..0]     = HBP_WXGA;
	HTOT50[11..0]  = HTOT50_WXGA;
	HTOT60[11..0]  = HTOT60_WXGA;
	HTOT75[11..0]  = HTOT75_WXGA; 
	HTOT90[11..0]  = HTOT90_WXGA;
	HTOT100[11..0] = HTOT100_WXGA;
	HTOT120[11..0] = HTOT120_WXGA;  

	VSY[10..0]     = VSY_WXGA;
	VBP[10..0]     = VBP_WXGA;
	VTOT50[10..0]  = VTOT50_WXGA;
	VTOT60[10..0]  = VTOT60_WXGA;
	VTOT75[10..0]  = VTOT75_WXGA;
	VTOT90[10..0]  = VTOT90_WXGA;
	VTOT100[10..0] = VTOT100_WXGA;
	VTOT120[10..0] = VTOT120_WXGA;
 
WHEN 1 =>                  -- 1024 x 768
%	HAC[10..0]     = HAC_XGA_pdp;
	VAC[10..0]     = VAC_XGA_pdp; 

	VPS_0[10..0]  = VPS_0_XGA_pdp;   
	VPS_1[10..0]  = VPS_1_XGA_pdp;
	VPS_2[10..0]  = VPS_2_XGA_pdp;
	VPS_3[10..0]  = VPS_3_XGA_pdp;

	HP1[10..0] = HP1_XGA_pdp; 
	HP2[10..0] = HP2_XGA_pdp;   
	HP3[10..0] = HP3_XGA_pdp;  
	VP1[10..0] = VP1_XGA_pdp;  
	VP2[10..0] = VP2_XGA_pdp; 
	VP3[10..0] = VP3_XGA_pdp; 
	
	HSY[10..0]     = HSY_XGA_pdp;
	HBP[10..0]     = HBP_XGA_pdp;
	HTOT50[11..0]  = HTOT50_XGA_pdp;
	HTOT60[11..0]  = HTOT60_XGA_pdp;
	HTOT75[11..0]  = HTOT75_XGA_pdp;
	HTOT90[11..0]  = HTOT90_XGA_pdp;
	HTOT100[11..0] = HTOT100_XGA_pdp;
	HTOT120[11..0] = HTOT120_XGA_pdp;		   
	
	VSY[10..0]     = VSY_XGA_pdp;
	VBP[10..0]     = VBP_XGA_pdp;
	VTOT50[10..0]  = VTOT50_XGA_pdp;
	VTOT60[10..0]  = VTOT60_XGA_pdp;
	VTOT75[10..0]  = VTOT75_XGA_pdp;
	VTOT90[10..0]  = VTOT90_XGA_pdp;
	VTOT100[10..0] = VTOT100_XGA_pdp;
	VTOT120[10..0] = VTOT120_XGA_pdp; 
%
	HAC[10..0]     = HAC_XGA;
	VAC[10..0]     = VAC_XGA; 

	VPS_0[10..0]  = VPS_0_XGA;   
	VPS_1[10..0]  = VPS_1_XGA;
	VPS_2[10..0]  = VPS_2_XGA;
	VPS_3[10..0]  = VPS_3_XGA;

	HP1[10..0] = HP1_XGA; 
	HP2[10..0] = HP2_XGA;   
	HP3[10..0] = HP3_XGA;  
	VP1[10..0] = VP1_XGA;  
	VP2[10..0] = VP2_XGA; 
	VP3[10..0] = VP3_XGA; 
	
	HSY[10..0]     = HSY_XGA;
	HBP[10..0]     = HBP_XGA;
	HTOT50[11..0]  = HTOT50_XGA;
	HTOT60[11..0]  = HTOT60_XGA;
	HTOT75[11..0]  = HTOT75_XGA;
	HTOT90[11..0]  = HTOT90_XGA;
	HTOT100[11..0] = HTOT100_XGA;
	HTOT120[11..0] = HTOT120_XGA;		   
	
	VSY[10..0]     = VSY_XGA;
	VBP[10..0]     = VBP_XGA;
	VTOT50[10..0]  = VTOT50_XGA;
	VTOT60[10..0]  = VTOT60_XGA;
	VTOT75[10..0]  = VTOT75_XGA;
	VTOT90[10..0]  = VTOT90_XGA;
	VTOT100[10..0] = VTOT100_XGA;
	VTOT120[10..0] = VTOT120_XGA; 

WHEN 2 =>					-- 1368 x 768
	HAC[10..0]     = HAC_1368x768;				
	VAC[10..0]     = VAC_1368x768; 
	
	VPS_0[10..0] = VPS_0_1368x768;   
	VPS_1[10..0] = VPS_1_1368x768;
	VPS_2[10..0] = VPS_2_1368x768;
	VPS_3[10..0] = VPS_3_1368x768;

	HP1[10..0] = HP1_1368x768; 
	HP2[10..0] = HP2_1368x768;   
	HP3[10..0] = HP3_1368x768;  
	VP1[10..0] = VP1_1368x768;  
	VP2[10..0] = VP2_1368x768; 
	VP3[10..0] = VP3_1368x768;
	
	HSY[10..0]     = HSY_1368x768;
	HBP[10..0]     = HBP_1368x768;
	HTOT50[11..0]  = HTOT50_1368x768;  
	HTOT60[11..0]  = HTOT60_1368x768;
	HTOT75[11..0]  = HTOT75_1368x768; 
	HTOT90[11..0]  = HTOT90_1368x768;  
	HTOT100[11..0] = HTOT100_1368x768;
	HTOT120[11..0] = HTOT120_1368x768;
			
	VSY[10..0]     = VSY_1368x768;
	VBP[10..0]     = VBP_1368x768;
	VTOT50[10..0]  = VTOT50_1368x768;
	VTOT60[10..0]  = VTOT60_1368x768;
	VTOT75[10..0]  = VTOT75_1368x768;
	VTOT90[10..0]  = VTOT90_1368x768;  
	VTOT100[10..0] = VTOT100_1368x768;
	VTOT120[10..0] = VTOT120_1368x768;

WHEN 3 =>                   -- 1280 x 1024
	HAC[10..0]     = HAC_SXGA;   
	VAC[10..0]     = VAC_SXGA; 
			
	VPS_0[10..0] = VPS_0_SXGA;   
	VPS_1[10..0] = VPS_1_SXGA;
	VPS_2[10..0] = VPS_2_SXGA;
	VPS_3[10..0] = VPS_3_SXGA;

	HP1[10..0] = HP1_SXGA; 
	HP2[10..0] = HP2_SXGA;   
	HP3[10..0] = HP3_SXGA;  
	VP1[10..0] = VP1_SXGA;  
	VP2[10..0] = VP2_SXGA; 
	VP3[10..0] = VP3_SXGA; 
	
	HSY[10..0]     = HSY_SXGA;
	HBP[10..0]     = HBP_SXGA;
	HTOT50[11..0]  = HTOT50_SXGA;
	HTOT60[11..0]  = HTOT60_SXGA;
	HTOT75[11..0]  = HTOT75_SXGA;
	HTOT90[11..0]  = HTOT90_SXGA;
	HTOT100[11..0] = HTOT100_SXGA;
	HTOT120[11..0] = HTOT120_SXGA;
			   
	VSY[10..0]     = VSY_SXGA;
	VBP[10..0]     = VBP_SXGA;
	VTOT50[10..0]  = VTOT50_SXGA;
	VTOT60[10..0]  = VTOT60_SXGA;
	VTOT75[10..0]  = VTOT75_SXGA;
	VTOT90[10..0]  = VTOT90_SXGA;
	VTOT100[10..0] = VTOT100_SXGA;
	VTOT120[10..0] = VTOT120_SXGA;