moving_object.vhd

基于fpga的屏幕测试程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.all;

ENTITY moving_object IS 
GENERIC(
	HAC		: integer  :=1280;
	VAC		: integer  :=1024;
	DST   	: integer  :=32;
	dataN   : integer  :=80;
	H_WIDTH : integer  :=160;
	V_WIDTH : integer  :=120;
	HBLOCK  : integer  :=100;
	VBLOCK  : integer  :=100;	
	HCE 	: integer  :=640;
	VCE 	: integer  :=512;
	LBAR    : integer  :=640-160;
	RBAR    : integer  :=640+160 
	);

PORT( 
  clk     	: IN  std_logic;
  clken   	: IN  std_logic; 		
  wren    	: IN  std_logic;		-- ram write enalbe
  reverse   : IN  std_logic;		-- reverse grayscales of back and front 
  vcount  	: IN  std_logic_vector(10 DOWNTO 0); -- vac counter
  hcount  	: IN  std_logic_vector(10 DOWNTO 0); -- hac counter
  back_red  : IN  std_logic_vector(7 DOWNTO 0);
  back_gre  : IN  std_logic_vector(7 DOWNTO 0); 
  back_blu  : IN  std_logic_vector(7 DOWNTO 0);
  front_red : IN  std_logic_vector(7 DOWNTO 0); 
  front_gre : IN  std_logic_vector(7 DOWNTO 0); 
  front_blu : IN  std_logic_vector(7 DOWNTO 0); 
  speed   	: IN  std_logic_vector(5 DOWNTO 0); 
  distance	: IN  std_logic_vector(3 DOWNTO 0); 
  delay     : IN  std_logic_vector(3 DOWNTO 0);	
  bar       : IN  std_logic_vector(3 DOWNTO 0);	
  address   : IN  std_logic_vector(8 DOWNTO 0);	-- address of simulation data down via i2c
  date_r    : IN  std_logic_vector(7 DOWNTO 0);	-- simulation data, with address down via i2c
  date_g    : IN  std_logic_vector(7 DOWNTO 0);	
  date_b    : IN  std_logic_vector(7 DOWNTO 0);	
  active    : OUT std_logic;
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);

END moving_object;

ARCHITECTURE rtl OF moving_object IS

SIGNAL nn				: integer RANGE 2047 DOWNTO -1024 ;
SIGNAL dist				: integer RANGE 511 DOWNTO 0 ;
SIGNAL count			: integer RANGE 127 DOWNTO 0 ;
SIGNAL countmax			: integer RANGE 511 DOWNTO 0 ;
SIGNAL count1			: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL barcolor			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL flag				: STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL mov_rdad_a		: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL mov_rdad_b		: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL mov_rdad7b_a		: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL mov_rdad7b_b		: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL sim_rdad_a		: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL sim_rdad_b		: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL sim_rdad9b_a		: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL sim_rdad9b_b		: STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL mov_data_r		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qa_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qb_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qa_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qb_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL back_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL front_r			: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL mov_data_g		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qa_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qb_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qa_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qb_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL back_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL front_g			: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL mov_data_b		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qa_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mov_qb_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qa_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sim_qb_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL back_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL front_b			: STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT sim_ram_r IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT sim_ram_g IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT sim_ram_b IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT mov_ram_r IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT mov_ram_g IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT mov_ram_b IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN

-- buffer storage for moving object data
u1_1: mov_ram_r
port map
	(  
		data		=>	mov_data_r,
		wraddress	=>	count1,
		rdaddress_a	=>	mov_rdad7b_a,
		rdaddress_b	=>	mov_rdad7b_b,
		wren		=>	'1',
		clock		=>	clk,
		qa	=>	mov_qa_r,
		qb	=>	mov_qb_r
	);
	
u1_2: mov_ram_g	
port map
	(  
		data		=>	mov_data_g,
		wraddress	=>	count1,
		rdaddress_a	=>	mov_rdad7b_a,
		rdaddress_b	=>	mov_rdad7b_b,
		wren		=>	'1',
		clock		=>	clk,
		qa	=>	mov_qa_g,
		qb	=>	mov_qb_g
	);
	
u1_3: mov_ram_b	
port map
	(  
		data		=>	mov_data_b,
		wraddress	=>	count1,
		rdaddress_a	=>	mov_rdad7b_a,
		rdaddress_b	=>	mov_rdad7b_b,
		wren		=>	'1',
		clock		=>	clk,
		qa	=>	mov_qa_b,
		qb	=>	mov_qb_b
	);
		
-- buffer storage for simulation data downloaded via i2c
u2_1: sim_ram_r
port map
	(  
		data		=>	date_r,
		wraddress	=>	address,
		rdaddress_a	=>	sim_rdad9b_a,
		rdaddress_b	=>	sim_rdad9b_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	sim_qa_r,
		qb	=>	sim_qb_r
	);
	
u2_2: sim_ram_g
port map
	(  
		data		=>	date_g,
		wraddress	=>	address,
		rdaddress_a	=>	sim_rdad9b_a,
		rdaddress_b	=>	sim_rdad9b_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	sim_qa_g,
		qb	=>	sim_qb_g
	);
	
u2_3: sim_ram_b
port map
	(  
		data		=>	date_b,
		wraddress	=>	address,
		rdaddress_a	=>	sim_rdad9b_a,
		rdaddress_b	=>	sim_rdad9b_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	sim_qa_b,
		qb	=>	sim_qb_b
	);		
-----------------------------------------------------------
-- travel distance of motion block
PROCESS(clk,distance)
BEGIN
IF clk'event AND clk='1' THEN
	CASE distance IS
		WHEN  "0000"=>	dist <= 0;
		WHEN  "0001"=>	dist <= DST*1;
		WHEN  "0010"=>	dist <= DST*2;
	    WHEN  "0011"=>	dist <= DST*3;
	    WHEN  "0100"=>	dist <= DST*4;
	    WHEN  "0101"=>	dist <= DST*5;
	    WHEN  "0110"=>	dist <= DST*6;
	    WHEN  "0111"=>	dist <= DST*7;
	    WHEN  "1000"=>	dist <= DST*8;
	    WHEN  "1001"=>	dist <= DST*9;
		WHEN  "1010"=>	dist <= DST*10;
		WHEN  "1011"=>	dist <= DST*11;
		WHEN  "1100"=>	dist <= DST*12;
		WHEN  "1101"=>	dist <= DST*13;
		WHEN  "1110"=>	dist <= DST*14;
		WHEN  "1111"=>	dist <= DST*15;
	    WHEN OTHERS =>	dist <= 0;
	END CASE;
END IF;	
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	back_r 	 <= back_red;
	front_r  <= front_red;
	back_g 	 <= back_gre;
	front_g  <= front_gre;
	back_b 	 <= back_blu;
	front_b  <= front_blu;
	barcolor <= bar&"0000";	--bar grayscale 16,32,64...
END IF;
END PROCESS;

--read simulation data from sim_ram
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	if hcount>=HCE-dataN and hcount<HCE+dataN
	then
		sim_rdad_a <= hcount-(HCE-dataN);
		sim_rdad_b <= hcount-(HCE-dataN);
	else
		sim_rdad_a <= "00000000000";
		sim_rdad_b <= "00000000000";
	end if;
END IF;
END PROCESS;

PROCESS (clk, sim_rdad_a, sim_rdad_b)
BEGIN
IF clk'event AND clk='1' THEN
	sim_rdad9b_a <= sim_rdad_a(8 downto 0); -- sim_rdad_a_8b -> sim_ram rdaddress
	sim_rdad9b_b <= sim_rdad_b(8 downto 0); -- sim_rdad_b_8b -> sim_ram rdaddress
END IF;
END PROCESS;

--write moving object data into mov_ram 
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	count1 <= count1+1;		-- counter with module=128
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	if count1<HBLOCK and reverse='0' then 
		mov_data_r <= front_r;				-- mov_data_r is written data of mov_ram
	    mov_data_g <= front_g;
	    mov_data_b <= front_b;
	 elsif count1<HBLOCK and reverse='1' then
	    mov_data_r <= back_r;
	    mov_data_g <= back_g;
		mov_data_b <= back_b;	
	 elsif count1>=HBLOCK and reverse='0' then 
	    mov_data_r <= back_r;
		mov_data_g <= back_g;
		mov_data_b <= back_b;
	 else
		mov_data_r <= front_r;
		mov_data_g <= front_g;	
		mov_data_b <= front_b;	
	end if ;
end IF;
END PROCESS;

--read moving object data from mov_ram
--countmax <= conv_integer(delay)*6;  --disappear time of the moving object
PROCESS(clk,delay)
BEGIN
IF clk'event AND clk='1' THEN
	CASE delay IS
		WHEN  "0000"=>	countmax <= 0;
		WHEN  "0001"=>	countmax <= 6;
		WHEN  "0010"=>	countmax <= 12;
	    WHEN  "0011"=>	countmax <= 18;
	    WHEN  "0100"=>	countmax <= 24;
	    WHEN  "0101"=>	countmax <= 30;
	    WHEN  "0110"=>	countmax <= 36;
	    WHEN  "0111"=>	countmax <= 48;
	    WHEN  "1000"=>	countmax <= 60;
	    WHEN  "1001"=>	countmax <= 72;
		WHEN  "1010"=>	countmax <= 90;
		WHEN  "1011"=>	countmax <= 120;
		WHEN  "1100"=>	countmax <= 180;
		WHEN  "1101"=>	countmax <= 240;
		WHEN  "1110"=>	countmax <= 300;
		WHEN  "1111"=>	countmax <= 360;
	    WHEN OTHERS =>	countmax <= 0;
	END CASE;
END IF;	
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	IF clken='1' THEN   --nn changes when every frame starts  
		IF nn>=HAC THEN   --nn:(390-dist)~~(790+dist)  --RBAR+dist
			if count=countmax then
				nn <= 0-HBLOCK;---dist;
				count <= 0;
			else 
				count <= count+1;
				nn <= HAC;
			end if;
		ELSE
			nn <= (nn+conv_integer(speed));
		END IF;
	END IF;
END IF;
END PROCESS;

PROCESS(clk,hcount,nn)
BEGIN
IF clk'event AND clk='1' THEN
	mov_rdad_a <= (hcount-nn);   --mov_rdad_a(6..0)->mov_rdad7b_a->mov_ram rdaddress
	mov_rdad_b <= (hcount-nn);   --mov_rdad_b(6..0)->mov_rdad7b_b->mov_ram rdaddress
END IF;
END PROCESS; 

PROCESS(clk,mov_rdad_a)
BEGIN
IF clk'event AND clk='1' THEN
	if  mov_rdad_a<HBLOCK then 
		mov_rdad7b_a <= mov_rdad_a(6 downto 0); -- mov_rdad7b_a->mov_ram rdaddress
	else mov_rdad7b_a <= "1111111";
	end if;
END IF;
END PROCESS;

PROCESS(clk,mov_rdad_b)
BEGIN
IF clk'event AND clk='1' THEN
	if  mov_rdad_b<HBLOCK then 
		mov_rdad7b_b <= mov_rdad_b(6 downto 0); -- mov_rdad7b_b->mov_ram rdaddress
	else mov_rdad7b_b <= "1111111";
	end if;
END IF;
END PROCESS;

--when in different positon flag will be set to different value
--flag
--00 background
--01 simulation data
--10 moving object
--11 bar data
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	if vcount>=VCE-25-VBLOCK AND vcount<VCE-25 then
		if bar(0)='0' then 
			flag<="10";
		 else flag<="01";
		end if;

	elsif (vcount>=VCE-25 AND vcount<VCE+25) or vcount>=VCE+VBLOCK+25  or vcount<VCE-VBLOCK-25 then 
		flag<="00";

	elsif  vcount>=VCE+25 AND vcount<VCE+VBLOCK+25 then
		if bar(0)='0' then 
			flag<="01";
		 else flag<="10";
		end if; 

	else 
		flag<="00";
	end if;
END IF;
END PROCESS;


PROCESS(clk,hcount,vcount)
BEGIN
IF clk'event AND clk='1' THEN
	if vcount>=VCE-V_WIDTH AND vcount<VCE+V_WIDTH AND 
	   hcount>=HCE-H_WIDTH AND hcount<HCE+H_WIDTH then
		active <= '1';
	else active <= '0';
	end if; 
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
	IF flag="01" THEN		--01 simulation data
		out_r_e <=sim_qa_r;
		out_g_e <=sim_qa_g;
		out_b_e <=sim_qa_b;
		out_r_o <=sim_qb_r;
		out_g_o <=sim_qb_g;
		out_b_o <=sim_qb_b;
	ELSIF flag="10" THEN	--10 moving object
		out_r_e <=mov_qa_r;
		out_g_e <=mov_qa_g;
		out_b_e <=mov_qa_b;
		out_r_o <=mov_qb_r;
		out_g_o <=mov_qb_g;
		out_b_o <=mov_qb_b;
	ELSIF reverse='0' THEN	--00 background
		out_r_e <=back_r;
		out_g_e <=back_g;
		out_b_e <=back_b;
		out_r_o <=back_r;
		out_g_o <=back_g;
		out_b_o <=back_b;
	ELSE
		out_r_e <=front_r;
		out_g_e <=front_g;
		out_b_e <=front_b;
		out_r_o <=front_r;
		out_g_o <=front_g;
		out_b_o <=front_b;
	END IF;
END IF;
END PROCESS;


END rtl;